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ISL9N312AD3 Datasheet(数据表) 5 Page - Fairchild Semiconductor

部件型号  ISL9N312AD3
说明  N-Channel Logic Level PWM Optimized UltraFET Trench Power MOSFETs
下载  11 Pages
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制造商  FAIRCHILD [Fairchild Semiconductor]
网页  http://www.fairchildsemi.com
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ISL9N312AD3 Datasheet(HTML) 5 Page - Fairchild Semiconductor

 
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ISL9N312AD3 / ISL9N312AD3ST Rev C
©2002 Fairchild Semiconductor Corporation
Figure 11. Capacitance vs Drain to Source
Voltage
Figure 12. Gate Charge Waveforms for Constant
Gate Currents
Figure 13. Switching Time vs Gate Resistance
Figure 14. Switching Time vs Gate Resistance
Typical Characteristic (Continued) T
C = 25°C unless otherwise noted
100
1000
0.1
1
10
30
2000
VDS, DRAIN TO SOURCE VOLTAGE (V)
CISS = CGS + CGD
COSS ≅ CDS + CGD
CRSS = CGD
VGS = 0V, f = 1MHz
0
2
4
6
8
10
010
20
30
Qg, GATE CHARGE (nC)
ID = 14A
WAVEFORMS IN
DESCENDING ORDER:
ID = 32A
VDD = 15V
0
50
100
200
10
20
30
40
50
RGS, GATE TO SOURCE RESISTANCE (Ω)
150
0
VGS = 4.5V, VDD = 15V, ID = 11A
tr
tf
td(OFF)
td(ON)
0
50
100
150
200
0
10
20304050
RGS, GATE TO SOURCE RESISTANCE (Ω)
td(OFF)
tf
td(ON)
tr
VGS = 10V, VDD = 15V, ID = 11A
Test Circuits and Waveforms
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
tP
VGS
0.01
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0




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