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ISL9N306AD3 Datasheet(数据表) 5 Page - Fairchild Semiconductor

部件型号  ISL9N306AD3
说明  N-Channel Logic Level PWM Optimized UltraFET Trench Power MOSFETs 30V, 50A, 6mΩ
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制造商  FAIRCHILD [Fairchild Semiconductor]
网页  http://www.fairchildsemi.com
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ISL9N306AD3 Datasheet(HTML) 5 Page - Fairchild Semiconductor

 
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©2003 Fairchild Semiconductor Corporation
ISL9N306AD3 / ISL9N306AD3ST Rev. B2
Figure 11. Capacitance vs Drain to Source
Voltage
Figure 12. Gate Charge Waveforms for Constant
Gate Currents
Figure 13. Switching Time vs Gate Resistance
Figure 14. Switching Time vs Gate Resistance
Typical Characteristic (Continued)
1000
0.1
1
10
5000
100
30
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 0V, f = 1MHz
CISS = CGS + CGD
COSS ≅ CDS + CGD
CRSS = CGD
0
2
4
6
8
10
0
10
2030
4050
60
Qg, GATE CHARGE (nC)
VDD = 15V
ID = 50A
ID = 25A
WAVEFORMS IN
DESCENDING ORDER:
ID = 5A
0
50
100
150
200
250
300
0
10
20304050
RGS, GATE TO SOURCE RESISTANCE (Ω)
VGS = 4.5V, VDD = 15V, ID = 16A
tr
td(ON)
tf
td(OFF)
0
100
200
300
400
500
0
1020304050
RGS, GATE TO SOURCE RESISTANCE (Ω)
td(OFF)
tr
td(ON)
tf
VGS = 10V, VDD = 15V, ID = 16A
Test Circuits and Waveforms
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
tP
VGS
0.01
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0




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