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ISL9N302AP3 Datasheet(数据表) 5 Page - Fairchild Semiconductor

部件型号  ISL9N302AP3
说明  N-Channel Logic Level PWM Optimized UltraFET Trench Power MOSFETs
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制造商  FAIRCHILD [Fairchild Semiconductor]
网页  http://www.fairchildsemi.com
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ISL9N302AP3 Datasheet(HTML) 5 Page - Fairchild Semiconductor

 
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©2002 Fairchild Semiconductor Corporation
Rev. B January 2002
Figure 11. Capacitance vs Drain to Source
Voltage
Figure 12. Gate Charge Waveforms for Constant
Gate Currents
Figure 13. Switching Time vs Gate Resistance
Figure 14. Switching Time vs Gate Resistance
Typical Characteristic (Continued)
1000
10000
0.1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
CISS = CGS + CGD
COSS ≅ CDS + CGD
CRSS = CGD
VGS = 0V, f = 1MHz
20000
500
30
0
2
4
6
8
10
50
100
150
200
250
Qg, GATE CHARGE (nC)
VDD = 15V
ID = 75A
ID = 28A
WAVEFORMS IN
DESCENDING ORDER:
0
0
200
400
600
800
1000
0
1020304050
RGS, GATE TO SOURCE RESISTANCE (Ω)
VGS = 4.5V, VDD = 15V, ID = 28A
tr
td(ON)
td(OFF)
tf
0
200
400
600
800
1000
1200
1400
10
20
30
40
50
RGS, GATE TO SOURCE RESISTANCE (Ω)
VGS = 10V, VDD = 15V, ID = 28A
td(ON)
tf
tr
0
td(OFF)
Test Circuits and Waveforms
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
tP
VGS
0.01
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0




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