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TPL5100DGSR 数据表(PDF) 3 Page - Texas Instruments |
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TPL5100DGSR 数据表(HTML) 3 Page - Texas Instruments |
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3 / 14 page  D0 D1 TPL5100 D2 VDD PGOOD DNC MOS_DRV TCAL GND DONE TPL5100 www.ti.com SNAS629B – JULY 2013 – REVISED AUGUST 2013 Connection Diagram Figure 3. Top View 10-Lead VSSOP Pin Descriptions Pin(s) Name Description Application Information 1 D0 Logic Input to set period delay (tDP) Connect to GND (low logic value) or to VDD (high logic value) 2 D1 Logic Input to set period delay (tDP) Connect to GND (low logic value) or to VDD (high logic value) 3 D2 Logic Input to set period delay (tDP) Connect to GND (low logic value) or to VDD (high logic value) 4 VDD Supply voltage 5 GND Ground 6 DONE Logic input for Watchdog functionality 7 TCAL Short duration pulse output for estimation of TPL5100 timer delay. 8 MOS_DRV Drives external MOSFET to power cycle the remaining system. 9 DNC Do Not Connect Leave this pin floating 10 PGOOD Digital power good input Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPL5100 |
类似零件编号 - TPL5100DGSR |
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类似说明 - TPL5100DGSR |
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