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TPL5000 数据表(PDF) 5 Page - Texas Instruments |
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TPL5000 数据表(HTML) 5 Page - Texas Instruments |
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5 / 15 page  TPL5000 www.ti.com SNAS628A – JULY 2013 – REVISED JULY 2013 Electrical Characteristics (1) Specifications with standard typeface are for TA =TJ = 25°C, VDD-GND=2.5V, unless otherwise stated. Symbol Parameter Conditions Min(2) Typ(3) Max(2) Units POWER SUPPLY IVDD Supply current(4) PGOOD = VDD 30 50 nA PGOOD = GND 12 nA TIMER tDP Timer Delay Period 1, 2, 4, 8, 10, 16, 32, s 64 Timer Delay drift over life time(5) 0.06 % Timer Delay drift over temperature 400 ppm/°C tCAL Calibration pulse width 14.063 15.625 17.188 ms tDP to tCAL matching error (6) VDD ≤ 3.0V 0.1 % tDONE DONE Pulse width (6) 100 ns tRSTn RSTn Pulse width 15.625 ms tWAKE WAKE Pulse width 31.25 ms DIGITAL LOGIC LEVELS VIH Logic High Threshold PGOOD, DONE 0.7xVDD V VIL Logic Low Threshold PGOOD, DONE 0.3xVDD V WAKE, TCAL VDD-0.3 V Iout = 100uA VOH Logic output High Level WAKE, TCAL VDD-0.7 V Iout = 1mA WAKE, TCAL 0.3 V Iout = -100uA VOL Logic output Low Level WAKE, TCAL 0.7 V Iout = -1mA VOLRSTn RSTn Logic output Low Level IOL= -1mA 0.3 V IOHRSTn RSTn High Level output current VOHRSTn=VDD 1 nA TIMING TCAL, RSTn, WAKE, DONE, PGOOD - Refer to Timing Diagram trTCAL Rise Time TCAL Capacitive load 15pF 50 ns tfTCAL, Fall Time TCAL Capacitive load 15pF 50 ns trRSTn, Rise Time RSTn Capacitive load 15pF, 4 ns Rpull-up 100Kohm tfRSTn, Fall Time RSTn Capacitive load 15pF, 50 ns Rpull-up 100Kohm trWAKE Rise Time WAKE Capacitive load 15pF 50 ns tfWAKE Fall Time WAKE Capacitive load 15pF 50 ns tDDONE DONE to RSTn or WAKE delay Min delay 100 ns Max delay tDP-5*tCAL ms tDTCAL TCAL to RSTn or WAKE delay tCAL/2 ms (1) Electrical Characteristics Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. (2) Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through correlations using statistical quality control (SQC) method. (3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped production material. (4) The supply current doesn’t take in account load and pull-up resistor current. Input pins are at GND or VDD. (5) Operational life time test procedure equivalent to10 years. (6) Guaranteed by design. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TPL5000 |
类似零件编号 - TPL5000 |
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类似说明 - TPL5000 |
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