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5AGXFB1G431C4N 数据表(PDF) 63 Page - Altera Corporation |
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5AGXFB1G431C4N 数据表(HTML) 63 Page - Altera Corporation |
63 / 82 page Chapter 2: Device Datasheet for Arria V Devices 2–35 Switching Characteristics February 2012 Altera Corporation Arria V Device Handbook Volume 1: Device Overview and Datasheet Figure 2–3 shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for a data rate less than 1.25 Gbps. DQS Logic Block and Memory Output Clock Jitter Specifications Table 2–32 lists the DQS phase shift error for Arria V devices. Table 2–33 lists the memory output clock jitter specifications for Arria V devices. Figure 2–3. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Less than 1.25 Gbps 0.1 UI P-P baud/1667 20 MHz Frequency Sinusoidal Jitter Amplitude 20db/dec Table 2–32. DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Arria V Devices—Preliminary (1), (2) Number of DQS Delay Buffer –C4 Speed Grade –C5, I5 Speed Grade –C6 Speed Grade Unit 257 58 74 ps Notes to Table 2–32: (1) The numbers are preliminary pending silicon characterization. (2) This error specification is the absolute maximum and minimum error. For example, skew on two DQS delay buffers in a –4 speed grade is 58 ps or ±29 ps. Table 2–33. Memory Output Clock Jitter Specification for Arria V Devices—Preliminary (1) (Part 1 of 2) Parameter Clock Network Symbol –4 Speed Grade –5 Speed Grade –6 Speed Grade Unit Min Max Min Max Min Max Clock period jitter Regional t JIT(per) –50 50 –55 55 –55 55 ps Cycle-to-cycle period jitter Regional t JIT(cc) –100 100 –110 110 –110 110 ps Duty cycle jitter Regional t JIT(duty) –50 50 –82.5 82.5 –82.5 82.5 ps Clock period jitter Global t JIT(per) –75 75 –82.5 82.5 –82.5 82.5 ps Cycle-to-cycle period jitter Global t JIT(cc) –150 150 –165 165 –165 165 ps |
类似零件编号 - 5AGXFB1G431C4N |
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类似说明 - 5AGXFB1G431C4N |
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