数据搜索系统,热门电子元器件搜索 |
|
5AGXFB1D627C4N 数据表(PDF) 71 Page - Altera Corporation |
|
5AGXFB1D627C4N 数据表(HTML) 71 Page - Altera Corporation |
71 / 82 page Chapter 2: Device Datasheet for Arria V Devices 2–43 Configuration Specification February 2012 Altera Corporation Arria V Device Handbook Volume 1: Device Overview and Datasheet AS Configuration Timing Figure 2–7 shows the timing waveform for the active serial (AS) x1 mode and AS x4 mode configuration timing. Table 2–41 lists the timing parameters for AS x1 and AS x4 configurations in Arria V devices. Figure 2–7. AS Configuration Timing Notes to Figure 2–7: (1) The AS scheme supports standard and fast POR delay (tPOR). For tPOR delay information, refer to the “POR Delay Specification” section in the Configuration, Design Security, and remote System Upgrades in Arria V Devices chapter. (2) If you are using AS x4 mode, this signal represents the AS_DATA[3..0] and EPCQ sends in 4-bits of data for each DCLK cycle. (3) The initialization clock can be from the internal oscillator or CLKUSR pin. (4) After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low. Read Address bit N - 1 bit N bit 1 bit 0 tCD2UM nSTATUS nCONFIG CONF_DONE nCSO DCLK AS_DATA0/ASDO AS_DATA1 (2) INIT_DONE (4) User I/O User Mode tPOR tDH tSU tCO (1) (3) Table 2–41. AS Timing Parameters for AS x1 and x4 Configurations in Arria V Devices—Preliminary (1), (2) Symbol Parameter Minimum Maximum Unit tCO DCLK falling edge to the AS_DATA0/ASDO output — 4 µs tSU Data setup time before the rising edge on DCLK 1.5 — ns tH Data hold time after the rising edge on DCLK 0— ns tCD2UM CONF_DONE high to user mode 175 437 µs tCD2CU CONF_DONE high to CLKUSR enabled 4 x maximum DCLK period — — tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (Tinit x CLKUSR period) —— Tinit Number of clock cycles required for device initialization 17,408 — Cycles Notes to Table 2–41: (1) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device. (2) The tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for PS mode listed in Table 2–43 on page 2–45. |
类似零件编号 - 5AGXFB1D627C4N |
|
类似说明 - 5AGXFB1D627C4N |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |