 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
5AGXFB1G427C4N 数据表(PDF) 14 Page - Altera Corporation |
|
||||||||||||||||||||||||||||||
5AGXFB1G427C4N 数据表(HTML) 14 Page - Altera Corporation |
|
|
14 / 82 page  1–8 Chapter 1: Overview for the Arria V Device Family Low-Power Serial Transceivers Arria V Device Handbook February 2012 Altera Corporation Volume 1: Device Overview and Datasheet PMA Support To prevent core and I/O noise from coupling into the transceivers, the PMA block is isolated from the rest of the chip, ensuring optimal signal integrity. The transceiver channels consist of the PMA, PCS, and clock networks. You can also use the unused receiver PMA channels as additional transmit PLLs. Table 1–5 lists the transceiver PMA features. PCS Support The Arria V core logic connects to the PCS through an 8-, 10-, 16-, 20-, 32-, or 40-bit interface, depending on the transceiver data rate and protocol. Arria V devices contain PCS hard IP to support PCIe Gen1 and Gen2, XAUI, GbE, Serial RapidIO® (SRIO), and CPRI protocols. All other standard and proprietary protocols from 611 Mbps to 6.5536 Gbps are supported through the custom double-width mode (up to 6.5536 Gbps) and custom single-width mode (up to 3.75 Gbps) transceiver PCS hard IP. A dedicated 80-bit interface to the core logic connects directly from the PMA, bypassing the PCS hard IP, to support all protocols beyond 6.5536 Gbps up to 10.3125 Gbps. Table 1–6 lists the transceiver PCS features. Table 1–5. Transceiver PMA Features for Arria V Devices Features Capability Backplane support Up to 16” FR4 PCB fabric drive capability at up to 6.5536 Gbps Chip-to-chip support Up to 10.3125 Gbps PLL-based clock recovery Superior jitter tolerance Programmable serializer and deserializer (SERDES) Flexible SERDES width Equalization and pre-emphasis Up to 6 dB of pre-emphasis and 4 dB of equalization Ring oscillator transmit PLLs 611 Mbps to 10.3125 Gbps Input reference clock range 27 MHz to 710 MHz Transceiver dynamic reconfiguration Allows reconfiguration of single channels without affecting operation of other channels Table 1–6. Transceiver PCS Features for Arria V Devices (Part 1 of 2) PCS Support (1) Data Rates (Gbps) Transmitter Data Path Receiver Data Path Custom single- and double-width modes 0.61 to ~6.5536 Phase compensation FIFO, byte serializer, and 8B/10B encoder Word aligner, 8B/10B decoder, byte deserializer, and phase compensation FIFO PCIe Gen1: x1, x2, x4, x8 PCIe Gen2: x1, x2, x4 (2) 2.5 and 5.0 The same as custom single- and double-width modes, plus PIPE 2.0 interface to the core logic The same as custom single- and double-width modes, plus rate match FIFO and PIPE 2.0 interface to the core logic GbE 1.25 The same as custom single- and double-width modes The same as custom single- and double-width modes, plus rate match FIFO |
类似零件编号 - 5AGXFB1G427C4N |
|
类似说明 - 5AGXFB1G427C4N |
|
|
链接网址 |
| 隐私政策 |
| ALLDATASHEETCN.COM |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
