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5AGXFB1G427C4N 数据表(PDF) 66 Page - Altera Corporation |
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5AGXFB1G427C4N 数据表(HTML) 66 Page - Altera Corporation |
66 / 82 page 2–38 Chapter 2: Device Datasheet for Arria V Devices Configuration Specification Arria V Device Handbook February 2012 Altera Corporation Volume 1: Device Overview and Datasheet FPP Configuration Timing This section describes the fast passive parallel (FPP) configuration timing parameters for Arria V devices. DCLK-to-DATA[] Ratio (r) for FPP Configuration FPP configuration requires a different DCLK-to-DATA[] ratio when you turn on encryption or the compression feature. Table 2–38 lists the DCLK-to-DATA[] ratio for each combination. FPP Configuration Timing when DCLK to DATA[] = 1 Figure 2–5 shows the timing waveform for a FPP configuration when using a MAX® II device as an external host. This timing waveform shows timing when the DCLK-to- DATA[] ratio is 1. 1 When you enable decompression or the design security feature, the DCLK-to-DATA[] ratio varies for FPP x8 and FPP x16. For the respective DCLK-to-DATA[] ratio, refer to Table 2–38. Table 2–38. DCLK-to-DATA[] Ratio for Arria V Devices (1) Configuration Scheme Encryption Compression DCLK-to-DATA[] ratio (r) FPP (8-bit wide) Off Off 1 On Off 1 Off On 2 On On 2 FPP (16-bit wide) Off Off 1 On Off 2 Off On 4 On On 4 Note to Table 2–38: (1) Depending on the DCLK-to-DATA[] ratio, the host must send a DCLK frequency that is r times the DATA[] rate in byte per second (Bps) or word per second (Wps). For example, in FPP x16 where the r is 2, the DCLK frequency must be 2 times the DATA[] rate in Wps. |
类似零件编号 - 5AGXFB1G427C4N |
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类似说明 - 5AGXFB1G427C4N |
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