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5AGXFB1G427C4N 数据表(PDF) 64 Page - Altera Corporation |
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5AGXFB1G427C4N 数据表(HTML) 64 Page - Altera Corporation |
64 / 82 page 2–36 Chapter 2: Device Datasheet for Arria V Devices Switching Characteristics Arria V Device Handbook February 2012 Altera Corporation Volume 1: Device Overview and Datasheet OCT Calibration Block Specifications Table 2–34 lists the OCT calibration block specifications for Arria V devices. Figure 2–4 shows the TRS_RT for dyn_term_ctrl and oe signals. Duty Cycle Distortion (DCD) Specifications Table 2–35 lists the worst-case DCD for Arria V devices. Duty cycle jitter Global t JIT(duty) –75 75 –90 90 –90 90 ps Note to Table 2–33: (1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard. Table 2–33. Memory Output Clock Jitter Specification for Arria V Devices—Preliminary (1) (Part 2 of 2) Parameter Clock Network Symbol –4 Speed Grade –5 Speed Grade –6 Speed Grade Unit Min Max Min Max Min Max Table 2–34. OCT Calibration Block Specifications for Arria V Devices—Preliminary Symbol Description Min Typ Max Unit OCTUSRCLK Clock required by OCT calibration blocks — — 20 MHz TOCTCAL Number of OCTUSRCLK clock cycles required for RS OCT /RT OCT calibration — 1000 — Cycles TOCTSHIFT Number of OCTUSRCLK clock cycles required for OCT code to shift out — 32 — Cycles TRS_RT Time required between the dyn_term_ctrl and oe signal transitions in a bidirectional I/O buffer to dynamically switch between RS OCT and RT OCT —2.5 — ns Figure 2–4. Timing Diagram for dyn_term_ctrl and oe Signals Table 2–35. Worst-Case DCD on Arria V I/O Pins—Preliminary Symbol –C4 Speed Grade –C5,I5 Speed Grade –C6 Speed Grade Unit Min Max Min Max Min Max Output Duty Cycle 45 55 45 55 45 55 % TRS_RT TRS_RT dyn_term_ctrl oe Tristate RX RX Tristate |
类似零件编号 - 5AGXFB1G427C4N |
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类似说明 - 5AGXFB1G427C4N |
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