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EP2A15 数据表(PDF) 30 Page - Altera Corporation |
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EP2A15 数据表(HTML) 30 Page - Altera Corporation |
30 / 36 page Page 30 Timing Information Enhanced Configuration (EPC) Devices Datasheet January 2012 Altera Corporation tECLK EXCLK input period — 10 — — ns tECLKH EXCLK input duty cycle high time 40% duty cycle 4 — — ns tECLKL EXCLK input duty cycle low time 40% duty cycle 4 — — ns tECLKR EXCLK input rise time 100 MHz — — 3 ns tECLKF EXCLK input fall time 100 MHz — — 3 ns tPOR (4) POR time 2 ms 1 2 3 ms 100 ms 70 100 120 ms Notes to Table 14: (1) To calculate tOH, use the following equation: tOH = 0.5 (DCLK period) - 2.5 ns. (2) This parameter is used for CRC error detection by the FPGA. (3) This parameter is used for CONF_DONE error detection by the EPC device. (4) The FPGA VCCINT ramp time should be less than 1 ms for 2-ms POR and it should be less than 70 ms for 100-ms POR. Table 14. EPC Device Configuration Parameters (Part 2 of 2) Symbol Parameter Condition Min Typ Max Unit |
类似零件编号 - EP2A15 |
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类似说明 - EP2A15 |
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