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EP2A15 数据表(PDF) 28 Page - Altera Corporation |
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EP2A15 数据表(HTML) 28 Page - Altera Corporation |
28 / 36 page Page 28 IEEE Std. 1149.1 (JTAG) Boundary-Scan Enhanced Configuration (EPC) Devices Datasheet January 2012 Altera Corporation You can also program the EPC devices using the Quartus II software, the Altera Programming Unit (APU), and the appropriate configuration device programming adapter. Table 12 lists which programming adapter to use with each EPC device. IEEE Std. 1149.1 (JTAG) Boundary-Scan The EPC device provides JTAG BST circuitry that complies with the IEEE Std. 1149.1-1990 specification. JTAG BST can be performed before or after configuration, but not during configuration. Figure 6 shows the timing requirements for the JTAG signals. Table 13 lists the timing parameters and values for the EPC device. Table 12. Programming Adapters Device Package Adapter EPC16 88-pin UFBGA PLMUEPC-88 100-pin PQFP PLMQEPC-100 EPC8 100-pin PQFP PLMQEPC-100 EPC4 100-pin PQFP PLMQEPC-100 Figure 6. JTAG Timing Waveforms TDO TCK tJPZX tJPCO tJPH tJPXZ tJCP tJPSU tJCL tJCH TDI TMS Signal to be Captured Signal to be Driven tJSZX tJSSU tJSH tJSCO tJSXZ Table 13. JTAG Timing Parameters and Values (Part 1 of 2) Symbol Parameter Min Max Unit tJCP TCK clock period 100 — ns tJCH TCK clock high time 50 — ns tJCL TCK clock low time 50 — ns tJPSU JTAG port setup time 20 — ns tJPH JTAG port hold time 45 — ns tJPCO JTAG port clock output — 25 ns tJPZX JTAG port high impedance to valid output — 25 ns |
类似零件编号 - EP2A15 |
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类似说明 - EP2A15 |
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