数据搜索系统,热门电子元器件搜索 |
|
EP2A15 数据表(PDF) 26 Page - Altera Corporation |
|
EP2A15 数据表(HTML) 26 Page - Altera Corporation |
26 / 36 page Page 26 Power Sequencing Enhanced Configuration (EPC) Devices Datasheet January 2012 Altera Corporation Power Sequencing Altera requires that you power-up the FPGA's VCCINT supply before the EPC device's POR expires. Power up needs to be controlled so that the EPC device’s OE signal goes high after the CONF _DONE signal is pulled low. If the EPC device exits POR before the FPGA is powered up, the CONF_DONE signal will be high because the pull-up resistor is holding this signal high. When the EPC device exits POR, OE is released and pulled high by a pull-up resistor. Since the EPC device samples the nCS signal on the rising edge of OE, it detects a high level on CONF_DONE and enters an idle mode. DATA and DCLK outputs will not toggle in this state and configuration will not begin. The EPC device will only exit this mode if it is powered down and then powered up correctly. 1 To ensure the EPC device enters configuration mode properly, you must ensure that the FPGA completes power-up before the EPC device exits POR. The pin-selectable POR time feature is useful for ensuring this power-up sequence. The EPC device has two POR settings—2 ms when PORSEL is set to a high level and 100 ms when PORSEL is set to a low level. For more margin, the 100-ms setting can be selected to allow the FPGA to power-up before configuration is attempted. Alternatively, a power-monitoring circuit or a power-good signal can be used to keep the FPGA’s nCONFIG pin asserted low until both supplies have stabilized. This ensures the correct power up sequence for successful configuration. Programming and Configuration File Support The Quartus II software provides programming support for the EPC device and automatically generates the .pof for the EPC4, EPC8, and EPC16 devices. In a multi-device project, the Quartus II software can combine the .sof for multiple ACEX 1K, APEX 20K, APEX II, Cyclone series, FLEX 10K, Mercury, and Stratix series FPGAs into one programming file for the EPC device. f For more information about generating programming files, refer to the Altera Enhanced Configuration Devices. EPC devices can be programmed in-system through the industry-standard 4-pin JTAG interface. The ISP feature in the EPC device provides ease in prototyping and updating FPGA functionality. After programming an EPC device in-system, FPGA configuration can be initiated by including the EPC device’s JTAG INIT_CONF instruction (refer to Table 11). |
类似零件编号 - EP2A15 |
|
类似说明 - EP2A15 |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |