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EP2A15 数据表(PDF) 24 Page - Altera Corporation |
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EP2A15 数据表(HTML) 24 Page - Altera Corporation |
24 / 36 page Page 24 Pin Description Enhanced Configuration (EPC) Devices Datasheet January 2012 Altera Corporation WP# Input Usually tied to VCC or GND on the board. The controller does not drive this pin because it could cause contention. Connection to VCC is recommended for faster block erase or programming times and to allow programming of the flash-bottom boot block, which is required when programming the device using the Quartus II software. This pin should be connected to VCC even when the external flash interface is not used. VCCW Supply Block erase, full-chip erase, word write, or lock-bit configuration power supply. Connect this pin to the 3.3-V VCC supply, even when you are not using the external flash interface. RY/BY# Open-Drain Output Flash asserts this pin when a write or erase operation is complete. This pin is not connected to the controller. RY/BY# is only available in Sharp flash-based EPC8 and EPC16. (2) Leave this pin floating when the external flash interface is not used. BYTE# Input Flash byte-enable pin and is only available for EPC devices in the 100-pin PQFP package. This pin must be connected to VCC on the board even when you are not using the external flash interface (the controller uses the flash in 16-bit mode). For Intel flash-based EPC device, this pin is connected to the VCCQ of the Intel flash die internally. Therefore, BYTE# must be connected directly to VCC without using any pull-up resistor. Notes to Table 9: (1) These pins can be driven to 12 V during production testing of the flash memory. Since the controller cannot tolerate the 12-V level, connections from the controller to these pins are not made internal to the package. Instead they are available as two separate pins. You must connect the two pins at the board level (for example, on the PCB, connect the C-WE# pin from controller to F-WE# pin from the flash memory). (2) For more information, refer to the PCN0506: Addition of Intel Flash Memory As Source For EPC4, EPC8 and EPC16 Enhanced Configuration Devices and Using the Intel Flash Memory-Based EPC4, EPC8 and EPC16 white paper. Table 10. JTAG Interface Pins and Other Required Controller Pins (Part 1 of 2) Pin Name Pin Type Description TDI Input JTAG data input pin. Connect this pin to VCC if the JTAG circuitry is not used. TDO Output JTAG data output pin. Do not connect this pin if the JTAG circuitry is not used (leave this pin floating). TCK Input JTAG clock pin. Connect this pin to GND if the JTAG circuitry is not used. TMS Input JTAG mode select pin. Connect this pin to VCC if the JTAG circuitry is not used. PGM[2..0] Input These three input pins select one of the eight pages of configuration data to configure the FPGAs in the system. Connect these pins on the board to select the page specified in the Quartus II software when generating the EPC device POF. PGM[2] is the MSB. The default selection is page 0; PGM[2..0]=000. These pins must not be left floating. Table 9. External Flash Interface Pins (Part 2 of 2) Pin Name Pin Type Description |
类似零件编号 - EP2A15 |
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类似说明 - EP2A15 |
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