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EP2A15 数据表(PDF) 20 Page - Altera Corporation |
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EP2A15 数据表(HTML) 20 Page - Altera Corporation |
20 / 36 page Page 20 Functional Description Enhanced Configuration (EPC) Devices Datasheet January 2012 Altera Corporation The controller chip features a programmable oscillator that can output four different frequencies. The various settings generate clock outputs at frequencies as high as 10, 33, 50, and 66 MHz. Table 7 lists the internal oscillator frequencies. Clock source, oscillator frequency, and clock divider (N) settings can be made in the Quartus II software, by accessing the Configuration Device Options inside the Device Settings window or the Convert Programming Files window. The same window can be used to select between the internal oscillator and the external clock (EXCLK) input pin as your configuration clock source. The default setting selects the internal oscillator at the 10 MHz setting as the clock source, with a divide factor of 1. f For more information about making the configuration clock source, frequency, and divider settings, refer to the Altera Enhanced Configuration Devices. Flash In-System Programming (ISP) The flash memory inside EPC devices can be programmed in-system using the JTAG interface and the external flash interface. JTAG-based programming is facilitated by the configuration controller in the EPC device. External flash interface programming requires an external processor or FPGA to control the flash. 1 The EPC device flash memory supports 100,000 erase cycles. JTAG-based Programming The IEEE Std. 1149.1 JTAG Boundary Scan is implemented in EPC devices to facilitate the testing of its interconnection and functionality. EPC devices also support the ISP mode. The EPC device is compliant with the IEEE Std. 1532 draft 2.0 specification. The JTAG unit of the configuration controller communicates directly with the flash memory. The controller processes the ISP instructions and performs the necessary flash operations. EPC devices support the maximum JTAG TCK frequency of 10 MHz. During JTAG-based ISP, the external flash interface is not available. Before the JTAG interface programs the flash memory, an optional JTAG instruction (PENDCFG) can be used to assert the FPGA’s nCONFIG pin (using the nINIT_CONF pin). This will keep the FPGA in reset and terminate any internal flash access. This function prevents contention on the flash pins when both JTAG ISP and an external FPGA or processor try to access the flash simultaneously. The nINIT_CONF pin is released when the initiate configuration (nINIT_CONF) JTAG instruction is updated. As a result, the FPGA is configured with the new configuration data stored in flash. You can add an initiate configuration (nINIT_CONF) JTAG instruction to your programming file in the Quartus II software by enabling the Initiate configuration after programming option in the Programmer options window (Options menu). Table 7. Internal Oscillator Frequencies Frequency Setting Min (MHz) Typ (MHz) Max (MHz) 10 6.4 8.0 10.0 33 21.0 26.5 33.0 50 32.0 40.0 50.0 66 42.0 53.0 66.0 |
类似零件编号 - EP2A15 |
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类似说明 - EP2A15 |
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