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EP2A15 数据表(PDF) 15 Page - Altera Corporation |
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EP2A15 数据表(HTML) 15 Page - Altera Corporation |
15 / 36 page Functional Description Page 15 Enhanced Configuration (EPC) Devices Datasheet January 2012 Altera Corporation Figure 4 shows an FPP configuration schematic with the external flash interface in use. Figure 4. FPP Configuration with External Flash Interface (1) Notes to Figure 4: (1) For external flash interface support in the EPC8 device, contact Altera Applications 24/7 Technical Support. (2) Pin A20 in EPC16 devices, pins A20 and A19 in EPC8 devices, and pins A20, A19, and A18 in EPC4 devices should be left floating. These pins should not be connected to any signal as they are NC pins. (3) In the 100-pin PQFP package, you must externally connect the following pins: C-A0 to F-A0, C-A1 to F-A1, C-A15 to F-A15, C-A16 to F-A16 , and BYTE# to V CC. Additionally, you must make the following pin connections in both 100-pin PQFP and 88-pin UFBGA packages: C-RP# to F-RP#, C-WE# to F-WE#, TM1 to V CC, TM0 to GND, and WP# to VCC. (4) For PORSEL, PGM[], and EXCLK pin connections, refer to Table 10 on page 24. (5) RY/BY# pin is only available for Sharp flash-based EPC8 and EPC16 devices. (6) To protect Intel Flash based EPC devices content, isolate the V CCW supply from VCC. For more information, refer to “Intel Flash-Based EPC Device Protection” on page 16. (4) (4) MSEL DCLK DATA[7..0] nSTATUS CONF_DONE nCONFIG VCC VCC GND nCE Stratix Series or APEX II Device WE# RP# A[20..0] RY/BY# CE# OE# DQ[15..0] PLD or Processor EPC Device DCLK DATA[7..0] OE nCS nINIT_CONF WE#C RP#C WE#F RP#F A[20..0] (2) RY/BY# (5) CE# OE# DQ[15..0] GND EXCLK WP# PORSEL PGM[2..0] TMO VCC VCCW BYTE# (3) TM1 C-A0 (3) C-A1 (3) C-A15 (3) C-A16 (3) A0-F A1-F A15-F A16-F n nCEO N.C. (4) (4) (4) VCC(6) |
类似零件编号 - EP2A15 |
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类似说明 - EP2A15 |
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