数据搜索系统,热门电子元器件搜索 |
|
EP2A15 数据表(PDF) 13 Page - Altera Corporation |
|
EP2A15 数据表(HTML) 13 Page - Altera Corporation |
13 / 36 page Functional Description Page 13 Enhanced Configuration (EPC) Devices Datasheet January 2012 Altera Corporation Table 5 lists the concurrent PS configuration modes supported in the EPC device. f For more information about configuration schematics and concurrent configurations, refer to the configuration chapter in the appropriate device handbook. External Flash Interface The EPC devices support external FPGA or processor access to its flash memory. The unused portions of the flash memory can be used by the external device to store code or data. This interface can also be used in systems that implement remote configuration capabilities. Configuration data within a particular configuration page can be updated using the external flash interface and the system could be reconfigured with the new FPGA image. This interface is also useful to store Nios boot code, application code, or both. f For more information about the Stratix remote configuration feature, refer to the Remote System Configuration with Stratix & Stratix GX Devices chapter in the Stratix Device Handbook. The address, data, and control ports of the flash memory are internally connected to the EPC device controller and external device pins. An external source can drive these external device pins to access the flash memory when the flash interface is available. This external flash interface is a shared bus interface with the configuration controller chip. The configuration controller is the primary bus master. Since there is no bus arbitration support, the external device can only access the flash interface when the controller has tri-stated its internal interface to the flash. Simultaneous access by the controller and the external device will cause contention, and result in configuration and programming failures. Since the internal flash interface is directly connected to the external flash interface pins, controller flash access cycles will toggle the external flash interface pins. The external device must be able to tri-state its flash interface during these operations and ignore transitions on the flash interface pins. 1 The external flash interface signals cannot be shared between multiple EPC devices because this causes contention during ISP and configuration. During these operations, the controller chips inside the EPC devices are actively accessing flash memory. Therefore, EPC devices do not support shared flash bus interfaces. Table 5. EPC Devices in PS Mode Mode Name Mode (n =) (1) Used Outputs Unused Outputs PS mode 1 DATA0 DATA[7..1] drive low Multi-device PS mode 2 DATA[1..0] DATA[7..2] drive low Multi-device PS mode 4 DATA[3..0] DATA[7..4] drive low Multi-device PS mode 8 DATA[7..0] — Note to Table 5: (1) This is the number of valid DATA outputs for each configuration mode. |
类似零件编号 - EP2A15 |
|
类似说明 - EP2A15 |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |