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5AGXFB1D427C4N 数据表(PDF) 78 Page - Altera Corporation |
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5AGXFB1D427C4N 数据表(HTML) 78 Page - Altera Corporation |
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78 / 82 page  2–50 Chapter 2: Device Datasheet for Arria V Devices Glossary Arria V Device Handbook February 2012 Altera Corporation Volume 1: Device Overview and Datasheet S Sampling window (SW) Timing Diagram—the period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position in the sampling window, as shown: Single-ended voltage referenced I/O standard The JEDEC standard for the SSTl and HSTL I/O defines both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. After the receiver input has crossed the AC value, the receiver changes to the new logic state. The new logic state is then maintained as long as the input stays beyond the AC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing, as shown: Single-Ended Voltage Referenced I/O Standard T tC High-speed receiver/transmitter input and output clock period. TCCS (channel- to-channel-skew) The timing difference between the fastest and slowest output edges, including the tCO variation and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure under SW in this table). tDUTY High-speed I/O block—Duty cycle on high-speed transmitter output clock. Timing Unit Interval (TUI) The timing budget allowed for skew, propagation delays, and the data sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w) tFALL Signal high-to-low transition time (80–20%) tINCCJ Cycle-to-cycle jitter tolerance on the PLL clock input tOUTPJ_IO Period jitter on the GPIO driven by a PLL tOUTPJ_DC Period jitter on the dedicated clock output driven by a PLL tRISE Signal low-to-high transition time (20–80%) U —— Table 2–48. Glossary Table (Part 3 of 4) Letter Subject Definitions Bit Time 0.5 x TCCS RSKM Sampling Window (SW) RSKM 0.5 x TCCS VIH(AC) VIH(DC) VREF VIL(DC) VIL(AC) VOH VOL VCCIO VSS |
类似零件编号 - 5AGXFB1D427C4N |
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类似说明 - 5AGXFB1D427C4N |
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