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5AGXFB1G631I4N 数据表(PDF) 72 Page - Altera Corporation

部件名 5AGXFB1G631I4N
功能描述  Arria V Device Handbook
Download  82 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

5AGXFB1G631I4N 数据表(HTML) 72 Page - Altera Corporation

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2–44
Chapter 2: Device Datasheet for Arria V Devices
Configuration Specification
Arria V Device Handbook
February 2012
Altera Corporation
Volume 1: Device Overview and Datasheet
Table 2–42 lists the internal clock frequency specification for the AS configuration
scheme.
PS Configuration Timing
Figure 2–8 shows the timing waveform for a passive serial (PS) configuration when
using a MAX II device or microprocessor as an external host.
Table 2–42. DCLK Frequency Specification in the AS Configuration Scheme—Preliminary (1), (2)
Minimum
Typical
Maximum
Unit
5.3
7.9
12.5
MHz
10.6
15.7
25.0
MHz
21.3
31.4
50.0
MHz
42.6
62.9
100.0
MHz
Notes to Table 2–42:
(1) This applies to the DCLK frequency specification when using the internal oscillator as the configuration clock source.
(2) The AS multi-device configuration scheme does not support DCLK frequency of 100 MHz.
Figure 2–8. PS Configuration Timing Waveform (1)
Notes to Figure 2–8:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels. When
nCONFIG
is pulled low, a reconfiguration cycle begins.
(2) After power up, the Arria V device holds nSTATUS low for the time of the POR delay.
(3) After power up, before and during configuration, CONF_DONE is low.
(4) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(5) DATA0 is available as a user I/O pin after configuration. The state of this pin depends on the dual-purpose pin settings in the Device and Pins
Option.
(6) To ensure a successful configuration, send the entire configuration data to the Arria V device. CONF_DONE is released high after the Arria V device
receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin initialization
and enter user mode.
(7) After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low.
nCONFIG
nSTATUS (2)
CONF_DONE (3)
DCLK
DATA0
User I/O
INIT_DONE (7)
Bit 0
Bit 1
Bit 2
Bit 3
Bit n
tCD2UM
tCF2ST1
tCF2CD
tCFG
tCH tCL
tDH
tDSU
tCF2CK
tSTATUS
tCLK
tCF2ST0
tST2CK
High-Z
User Mode
(5)
(4)
(6)


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