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5AGXFB1D631I4N 数据表(PDF) 62 Page - Altera Corporation |
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5AGXFB1D631I4N 数据表(HTML) 62 Page - Altera Corporation |
62 / 82 page 2–34 Chapter 2: Device Datasheet for Arria V Devices Switching Characteristics Arria V Device Handbook February 2012 Altera Corporation Volume 1: Device Overview and Datasheet Table 2–30 lists the DPA lock time specifications for Arria V devices. Figure 2–2 shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for a data rate equal to 1.25 Gbps. Table 2–31 lists the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for a data rate equal to 1.25 Gbps. Table 2–30. DPA Lock Time Specifications for Arria V Devices—Preliminary (1), (2), (3) Standard Training Pattern Number of Data Transitions in One Repetition of the Training Pattern Number of Repetitions per 256 Data Transitions (4) Maximum SPI-4 00000000001111111111 2 128 640 data transitions Parallel Rapid I/O 00001111 2 128 640 data transitions 10010000 4 64 640 data transitions Miscellaneous 10101010 8 32 640 data transitions 01010101 8 32 640 data transitions Notes to Table 2–30: (1) The DPA lock time is for one channel. (2) One data transition is defined as a 0-to-1 or 1-to-0 transition. (3) The DPA lock time stated in this table applies to both commercial and industrial grades. (4) This is the number of repetitions for the stated training pattern to achieve the 256 data transitions. Figure 2–2. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Equal to 1.25 Gbps LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification F1 F2 F3 F4 Jitter Frequency (Hz) 0.1 0.35 8.5 25 Table 2–31. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.25 Gbps—Preliminary Jitter Frequency (Hz) Sinusoidal Jitter (UI) F1 10,000 25.000 F2 17,565 25.000 F3 1,493,000 0.350 F4 50,000,000 0.350 |
类似零件编号 - 5AGXFB1D631I4N |
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类似说明 - 5AGXFB1D631I4N |
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