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5AGXFB1G431I4N 数据表(PDF) 70 Page - Altera Corporation |
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5AGXFB1G431I4N 数据表(HTML) 70 Page - Altera Corporation |
70 / 82 page 2–42 Chapter 2: Device Datasheet for Arria V Devices Configuration Specification Arria V Device Handbook February 2012 Altera Corporation Volume 1: Device Overview and Datasheet Table 2–40 lists the timing parameters for Arria V devices when the DCLK -to-DATA[]ratio is more than 1. Table 2–40. DCLK-to-DATA[] FPP Timing Parameters for Arria V Devices When the Ratio is >1—Preliminary (1) Symbol Parameter Minimum Maximum Unit tCF2CD nCONFIG low to CONF_DONE low — 600 ns tCF2ST0 nCONFIG low to nSTATUS low — 600 ns tCFG nCONFIG low pulse width 2 — µs tSTATUS nSTATUS low pulse width 268 1506 (2) µs tCF2ST1 nCONFIG high to nSTATUS high — 1506 (3) µs tCF2CK nCONFIG high to first rising edge on DCLK 1506 — µs tST2CK nSTATUS high to first rising edge of DCLK 2— µs tDSU DATA[] setup time before rising edge on DCLK 5.5 — ns tDH DATA[] hold time after rising edge on DCLK 3 x 1/fDCLK —ns tCH DCLK high time 0.45 x 1/fMAX —ns tCL DCLK low time 0.45 x 1/fMAX —ns tCLK DCLK period 1/fMAX —ns fMAX DCLK frequency (FPP x8/ x16) — 125 MHz tR Input rise time — 40 ns tF Input fall time — 40 ns tCD2UM CONF_DONE high to user mode (4) 175 437 µs tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK period — — tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (Tinit x CLKUSR period) —— Tinit Number of clock cycles required for device initialization 17,408 — Cycles Notes to Table 2–40: (1) Use these timing parameters when you use decompression and the design security features. (2) This value can be obtained if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. (3) This value can be obtained if you do not delay configuration by externally holding nSTATUS low. (4) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device. |
类似零件编号 - 5AGXFB1G431I4N |
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类似说明 - 5AGXFB1G431I4N |
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