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5AGXFB1D431I4N 数据表(PDF) 55 Page - Altera Corporation |
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5AGXFB1D431I4N 数据表(HTML) 55 Page - Altera Corporation |
55 / 82 page Chapter 2: Device Datasheet for Arria V Devices 2–27 Switching Characteristics February 2012 Altera Corporation Arria V Device Handbook Volume 1: Device Overview and Datasheet Core Performance Specifications This section describes the clock tree, phase-locked loop (PLL), digital signal processing (DSP), memory blocks and temperature sensing diode specifications. Clock Tree Specifications Table 2–24 lists the clock tree specifications for Arria V devices. PLL Specifications Table 2–25 lists the Arria V PLL specifications when operating in both the commercial junction temperature range (0° to 85°C) and the industrial junction temperature range (–40° to 100°C). Table 2–24. Clock Tree Performance for Arria V Devices—Preliminary Performance Unit Symbol –C4 Speed Grade –C5, I5 Speed Grade –C6 Speed Grade Global clock and Regional clock 625 625 525 MHz Peripheral clock 450 400 350 MHz Table 2–25. PLL Specifications for Arria V Devices—Preliminary (1) (Part 1 of 3) Symbol Parameter Min Typ Max Unit fIN Input clock frequency (–4 speed grade) 5 — 670 (2) MHz Input clock frequency (–5 speed grade) 5 — 622 (2) MHz Input clock frequency (–6 speed grade) 5 — 500 (2) MHz fINPFD Integer input clock frequency to the PFD 5 — 325 MHz fFINPFD Fractional input clock frequency to the PFD 50 — TBD (1) MHz fVCO PLL VCO operating range (–4 speed grade) 600 — 1600 MHz PLL VCO operating range (–5 speed grade) 600 — 1400 MHz PLL VCO operating range (–6 speed grade) 600 — 1300 MHz tEINDUTY Input clock or external feedback clock input duty cycle 40 — 60 % fOUT Output frequency for internal global or regional clock (–4 speed grade) — — 500 (3) MHz Output frequency for internal global or regional clock (–5 speed grade) — — 500 (3) MHz Output frequency for internal global or regional clock (–6 speed grade) — — 400 (3) MHz fOUT_EXT Output frequency for external clock output (–4 speed grade) — — 670 (3) MHz Output frequency for external clock output (–5 speed grade) — — 622 (3) MHz Output frequency for external clock output (–6 speed grade) — — 500 (3) MHz tOUTDUTY Duty cycle for external clock output (when set to 50%) 45 50 55 % tFCOMP External feedback clock compensation time — — 10 ns tCONFIGPHASE Time required to reconfigure phase shift — — TBD (1) — tDYCONFIGCLK Dynamic Configuration Clock — — 100 MHz |
类似零件编号 - 5AGXFB1D431I4N |
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类似说明 - 5AGXFB1D431I4N |
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