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DP83848I Datasheet(数据表) 10 Page - Texas Instruments

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部件型号  DP83848I
说明  DP83848I PHYTER Industrial Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
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DP83848I Datasheet(HTML) 10 Page - Texas Instruments

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1.0 Pin Descriptions
The DP83848I pins are classified into the following inter-
face categories (each interface is described in the sections
that follow):
— Serial Management Interface
— MAC Data Interface
— Clock Interface
— LED Interface
—JTAG Interface
— Reset and Power Down
— Strap Options
— 10/100 Mb/s PMD Interface
— Special Connect Pins
— Power and Ground pins
Note: Strapping pin option. Please see Section 1.7 for strap
definitions.
All DP83848I signal pins are I/O cells regardless of the par-
ticular use. The definitions below define the functionality of
the I/O cells for each pin.
1.1 Serial Management Interface
1.2 MAC Data Interface
Type: I
Input
Type: O
Output
Type: I/O
Input/Output
Type OD
Open Drain
Type: PD,PU Internal Pulldown/Pullup
Type: S
Strapping Pin (All strap pins have weak in-
ternal pull-ups or pull-downs. If the default
strap value is needed to be changed then an
external 2.2 k
Ω resistor should be used.
Please see Section 1.7 for details.)
Signal Name
Type
Pin #
Description
MDC
I
31
MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO
management data input/output serial interface which may be
asynchronous to transmit and receive clocks. The maximum clock
rate is 25 MHz with no minimum clock rate.
MDIO
I/O
30
MANAGEMENT DATA I/O: Bi-directional management instruc-
tion/data signal that may be sourced by the station management
entity or the PHY. This pin requires a 1.5 k
Ω pullup resistor.
Signal Name
Type
Pin #
Description
TX_CLK
O
1
MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100
Mb/s mode or 2.5 MHz in 10 Mb/s mode derived from the 25 MHz
reference clock.
Unused in RMII mode. The device uses the X1 reference clock in-
put as the 50 MHz reference for both transmit and receive.
SNI TRANSMIT CLOCK: 10 MHz Transmit clock output in 10 Mb
SNI mode. The MAC should source TX_EN and TXD_0 using this
clock.
TX_EN
I, PD
2
MII TRANSMIT ENABLE: Active high input indicates the pres-
ence of valid data inputs on TXD[3:0].
RMII TRANSMIT ENABLE: Active high input indicates the pres-
ence of valid data on TXD[1:0].
SNI TRANSMIT ENABLE: Active high input indicates the pres-
ence of valid data on TXD_0.
TXD_0
TXD_1
TXD_2
TXD_3
I
S, I, PD
3
4
5
6
MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0],
that accept data synchronous to the TX_CLK (2.5 MHz in 10 Mb/s
mode or 25 MHz in 100 Mb/s mode).
RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0],
that accept data synchronous to the 50 MHz reference clock.
SNI TRANSMIT DATA: Transmit data SNI input pin, TXD_0, that
accept data synchronous to the TX_CLK (10 MHz in 10 Mb/s SNI
mode).




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