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FW21154AE 数据表(PDF) 21 Page - Intel Corporation |
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FW21154AE 数据表(HTML) 21 Page - Intel Corporation |
21 / 36 page 21154 PCI-to-PCI Bridge Specification Update Intel Confidential21 Errata corrupted resulting in a mismatch when the transaction is retried causing the transaction to be retried continuously. The primary master timeout timer times out (2 10 or 215 clock cycles), discards the data, and reinitiates the transaction on the next cycle. This transaction usually completes as a normal delayed read transaction. Since the 21154 is a highly symmetrical device and the CAM circuitry is duplicated on both the primary and secondary interfaces the issue may occur on either an upstream or downstream delayed read transactions. Implication: Applications using P_VIO and/or S_VIO=3.3V may experience excessive retries due to a reduction in noise immunity in the CAM section of the chip. When P_VIO and/or S_VIO is set above ~3.8V the biasing of the input transistor effectively reduces the resulting core ground undershoot that is coupled through the ESD protection clamp. This issue has only been reported in a very small number of high performance applications such as Video cards, Gigabit Ethernet and 100MByte/s Fibre Channel with P_VIO and/or S_VIO set to 3.3V. Other lower performance applications and implementations with P_VIO and S_VIO set to 5V have not reported the issue. This may also manifest as a layout sensitivity issue. Workaround: Setting P_VIO and S_VIO to 5V has proven to eliminate these issues on current designs. Many 21154 designs that implemented the errata 4 work around are already biasing the P_VIO and S_VIO pins to 5V and should not experience the issues. Note:P_VIO and S_VIO pins set the value of the voltage clamp only and has no affect on the signaling levels of the bus. Status: No Fix 10. Secondary Address pins are driven incorrectly during reset. Problem: During reset S_AD <63:0>, C/BE# and PAR are driven high. The PCI Local Bus Specification requires that these pins be driven low during reset. Implication: In applications where multiple PCI components implemented on the secondary bus may drive the bus during reset, there is a potential for device contention if the 21154AE/BE is driving high and the other device/devices are driving low. This contention may cause excessive power dissipation in the 21154 and could potentially damage the device. Workaround: There is no known work around. Status: No Fix |
类似零件编号 - FW21154AE |
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类似说明 - FW21154AE |
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