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EG80C188XL25 数据表(PDF) 13 Page - Intel Corporation |
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EG80C188XL25 数据表(HTML) 13 Page - Intel Corporation |
13 / 48 page 80C186XL80C188XL Table 3 Pin Descriptions (Continued) Pin Pin Input Output Pin Description Name Type Type States SRDY I S(L) Synchronous Ready informs the processor that the addressed memory space or IO device will complete a data transfer The SRDY pin accepts an active-HIGH input synchronized to CLKOUT The use of SRDY allows a relaxed system timing over ARDY This is accomplished by elimination of the one-half clock cycle required to internally synchonize the ARDY input signal Connecting SRDY high will always assert the ready condition to the CPU If this line is unused it should be tied LOW to yield control to the ARDY pin LOCK O H(Z) LOCK output indicates that other system bus masters are not to gain control of the system bus LOCK is active LOW The LOCK R(Z) signal is requested by the LOCK prefix instruction and is activated at the beginning of the first data cycle associated with the instruction immediately following the LOCK prefix It remains active until the completion of that instruction No instruction prefetching will occur while LOCK is asserted S0 O H(Z) Bus cycle status S0 –S2 are encoded to provide bus-transaction information S1 R(1) S2 Bus Cycle Status Information S2 S1 S0 Bus Cycle Initiated 0 0 0 Interrupt Acknowledge 0 0 1 Read IO 0 1 0 Write IO 0 1 1 Halt 1 0 0 Instruction Fetch 1 0 1 Read Data from Memory 1 1 0 Write Data to Memory 1 1 1 Passive (no bus cycle) S2 may be used as a logical MIO indicator and S1 as a DTR indicator HOLD I A(L) HOLD indicates that another bus master is requesting the local bus The HOLD input is active HIGH The processor generates HLDA HLDA O H(1) (HIGH) in response to a HOLD request Simultaneous with the R(0) issuance of HLDA the processor will float the local bus and control lines After HOLD is detected as being LOW the processor will lower HLDA When the processor needs to run another bus cycle it will again drive the local bus and control lines In Enhanced Mode HLDA will go low when a DRAM refresh cycle is pending in the processor and an external bus master has control of the bus It will be up to the external master to relinquish the bus by lowering HOLD so that the processor may execute the refresh cycle NOTE Pin names in parentheses apply to the 80C188XL 13 |
类似零件编号 - EG80C188XL25 |
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类似说明 - EG80C188XL25 |
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