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EG80C188XL20 数据表(PDF) 12 Page - Intel Corporation

部件名 EG80C188XL20
功能描述  16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
Download  48 Pages
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制造商  INTEL [Intel Corporation]
网页  http://www.intel.com
标志 INTEL - Intel Corporation

EG80C188XL20 数据表(HTML) 12 Page - Intel Corporation

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80C186XL80C188XL
Table 3 Pin Descriptions
(Continued)
Pin
Pin
Input
Output
Pin Description
Name
Type
Type
States
BHE
O
H(Z)
The BHE (Bus High Enable) signal is analogous to A0 in that it is
used to enable data on to the most significant half of the data bus
(RFSH)
R(Z)
pins D15 – D8 BHE will be LOW during T1 when the upper byte is
transferred and will remain LOW through T3 and TW BHE does not
need to be latched On the 80C188XL RFSH is asserted LOW to
indicate a refresh bus cycle
In Enhanced Mode BHE (RFSH) will also be used to signify DRAM
refresh cycles A refresh cycle is indicated by both BHE (RFSH) and
A0 being HIGH
80C186XL BHE and A0 Encodings
BHE
A0
Function
Value
Value
0
0
Word Transfer
0
1
Byte Transfer on upper half of data bus
(D15 – D8)
1
0
Byte Transfer on lower half of data bus (D7–D0)
1
1
Refresh
ALEQS0
O
H(0)
Address Latch EnableQueue Status 0 is provided by the processor
to latch the address ALE is active HIGH with addresses guaranteed
R(0)
valid on the trailing edge
WR QS1
O
H(Z)
Write StrobeQueue Status 1 indicates that the data on the bus is to
be written into a memory or an IO device It is active LOW When
R(Z)
the processor is in Queue Status Mode the ALEQS0 and WR QS1
pins provide information about processorinstruction queue
interaction
QS1
QS0
Queue Operation
0
0
No queue operation
0
1
First opcode byte fetched from the queue
1
1
Subsequent byte fetched from the queue
1
0
Empty the queue
RD QSMD
O
H(Z)
Read Strobe is an active LOW signal which indicates that the
processor is performing a memory or IO read cycle It is guaranteed
R(1)
not to go LOW before the AD bus is floated An internal pull-up
ensures that RD QSMD is HIGH during RESET Following RESET
the pin is sampled to determine whether the processor is to provide
ALE RD and WR or queue status information To enable Queue
Status Mode RD must be connected to GND
ARDY
I
A(L)
Asynchronous Ready informs the processor that the addressed
memory space or IO device will complete a data transfer The
S(L)
ARDY pin accepts a rising edge that is asynchronous to CLKOUT
and is active HIGH The falling edge of ARDY must be synchronized
to the processor clock Connecting ARDY HIGH will always assert
the ready condition to the CPU If this line is unused it should be tied
LOW to yield control to the SRDY pin
NOTE
Pin names in parentheses apply to the 80C188XL
12


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