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EG80C188XL20 数据表(PDF) 11 Page - Intel Corporation

部件名 EG80C188XL20
功能描述  16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
Download  48 Pages
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制造商  INTEL [Intel Corporation]
网页  http://www.intel.com
标志 INTEL - Intel Corporation

EG80C188XL20 数据表(HTML) 11 Page - Intel Corporation

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80C186XL80C188XL
Table 3 Pin Descriptions
(Continued)
Pin
Pin
Input
Output
Pin Description
Name
Type
Type
States
TMR IN 0
I
A(L)
Timer Inputs are used either as clock or control signals
depending upon the programmed timer mode These
TMR IN 1
A(E)
inputs are active HIGH (or LOW-to-HIGH transitions are
counted) and internally synchronized Timer Inputs must
be tied HIGH when not being used as clock or retrigger
inputs
TMR OUT 0
O
H(Q)
Timer outputs are used to provide single pulse or
continuous waveform generation depending upon the
TMR OUT 1
R(1)
timer mode selected These outputs are not floated
during a bus hold
DRQ0
I
A(L)
DMA Request is asserted HIGH by an external device
when it is ready for DMA Channel 0 or 1 to perform a
DRQ1
transfer These signals are level-triggered and internally
synchronized
NMI
I
A(E)
The Non-Maskable Interrupt input causes a Type 2
interrupt An NMI transition from LOW to HIGH is
latched and synchronized internally and initiates the
interrupt at the next instruction boundary NMI must be
asserted for at least one CLKOUT period The Non-
Maskable Interrupt cannot be avoided by programming
INT0
I
A(E)
Maskable Interrupt Requests can be requested by
activating one of these pins When configured as inputs
INT1SELECT
A(L)
these pins are active HIGH Interrupt Requests are
INT2INTA0
IO
A(E)
H(1)
synchronized internally INT2 and INT3 may be
INT3INTA1 IRQ
A(L)
R(Z)
configured to provide active-LOW interrupt-
acknowledge output signals All interrupt inputs may be
configured to be either edge- or level-triggered To
ensure recognition all interrupt requests must remain
active until the interrupt is acknowledged When Slave
Mode is selected the function of these pins changes
(see Interrupt Controller section of this data sheet)
A19S6
O
H(Z)
Address Bus Outputs and Bus Cycle Status (3 – 6)
indicate the four most significant address bits during T1
A18S5
R(Z)
These signals are active HIGH
A17S4
A16S3
During T2 T3 TW and T4 the S6 pin is LOW to indicate
a CPU-initiated bus cycle or HIGH to indicate a DMA-
(A8 – A15)
initiated or refresh bus cycle During the same T-states
S3 S4 and S5 are always LOW On the 80C188XL
A15 – A8 provide valid address information for the entire
bus cycle
AD0 – AD15
IO
S(L)
H(Z)
AddressData Bus signals constitute the time
multiplexed memory or IO address (T1) and data (T2
(AD0 – AD7)
R(Z)
T3 TW and T4) bus The bus is active HIGH For the
80C186XL A0 is analogous to BHE for the lower byte of
the data bus pins D7 through D0 It is LOW during T1
when a byte is to be transferred onto the lower portion
of the bus in memory or IO operations
NOTE
Pin names in parentheses apply to the 80C188XL
11


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