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EG80C188XL20 数据表(PDF) 8 Page - Intel Corporation

部件名 EG80C188XL20
功能描述  16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
Download  48 Pages
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制造商  INTEL [Intel Corporation]
网页  http://www.intel.com
标志 INTEL - Intel Corporation

EG80C188XL20 数据表(HTML) 8 Page - Intel Corporation

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80C186XL80C188XL
PACKAGE INFORMATION
This section describes the pin functions pinout and
thermal characteristics for the 80C186XL in the
Quad Flat Pack (QFP) Plastic Leaded Chip Carrier
(PLCC) Leadless Chip Carrier (LCC) and the Shrink
Quad Flat Pack (SQFP) For complete package
specifications and information see the Intel Packag-
ing Outlines and Dimensions Guide (Order Number
231369)
Pin Descriptions
Each pin or logical set of pins is described in Table
3 There are four columns for each entry in the Pin
Description Table The following sections describe
each column
Column 1 Pin Name
In this column is a mnemonic that de-
scribes the pin function Negation of the
signal name (ie
RESIN) implies that
the signal is active low
Column 2 Pin Type
A pin may be either power (P) ground
(G) input only (I) output only (O) or in-
putoutput (IO) Please note that some
pins have more than one function
Column 3 Input Type (for I and IO types only)
These are two different types of input
pins on the 80C186XL asynchronous
and synchronous Asynchronous pins
require that setup and hold times be met
only to
guarantee recognition Synchro-
nous
input pins require that the setup
and hold times be met to
guarantee
proper operation Stated simply missing
a setup or hold on an asynchronous pin
will result in something minor (ie a tim-
er count will be missed) whereas miss-
ing a setup or hold on a synchronous pin
result in system failure (the system will
‘‘lock up’’)
An input pin may also be edge or level
sensitive
Column 4 Output States (for O and IO types
only)
The state of an output or IO pin is de-
pendent on the operating mode of the
device There are four modes of opera-
tion that are different from normal active
mode Bus Hold Reset Idle Mode Pow-
erdown Mode This column describes
the output pin state in each of these
modes
The legend for interpreting the information in the Pin
Descriptions is shown in Table 2
As an example please refer to the table entry for
AD70 The ‘‘IO’’ signifies that the pins are bidirec-
tional (ie have both an input and output function)
The ‘‘S’’ indicates that as an input the signal must
be synchronized to CLKOUT for proper operation
The ‘‘H(Z)’’ indicates that these pins will float while
the processor is in the Hold Acknowledge state
R(Z) indicates that these pins will float while RESIN
is low
All pins float while the processor is in the ONCE
Mode (with the exception of X2)
8


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