数据搜索系统,热门电子元器件搜索
  Chinese  ▼

Delete All
ON OFF
ALLDATASHEETCN.COM

X  

预览 PDF Download HTML

EG80C188XL20 数据表(PDF) 7 Page - Intel Corporation

部件名 EG80C188XL20
功能描述  16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
Download  48 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  INTEL [Intel Corporation]
网页  http://www.intel.com
标志 INTEL - Intel Corporation

EG80C188XL20 数据表(HTML) 7 Page - Intel Corporation

Back Button EG80C188XL20 Datasheet HTML 3Page - Intel Corporation EG80C188XL20 Datasheet HTML 4Page - Intel Corporation EG80C188XL20 Datasheet HTML 5Page - Intel Corporation EG80C188XL20 Datasheet HTML 6Page - Intel Corporation EG80C188XL20 Datasheet HTML 7Page - Intel Corporation EG80C188XL20 Datasheet HTML 8Page - Intel Corporation EG80C188XL20 Datasheet HTML 9Page - Intel Corporation EG80C188XL20 Datasheet HTML 10Page - Intel Corporation EG80C188XL20 Datasheet HTML 11Page - Intel Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 48 page
background image
80C186XL80C188XL
DRAM Refresh Control Unit
The Refresh Control Unit (RCU) automatically gen-
erates DRAM refresh bus cycles The RCU operates
only in Enhanced Mode After a programmable peri-
od of time the RCU generates a memory read re-
quest to the BIU If the address generated during a
refresh bus cycle is within the range of a properly
programmed chip select that chip select will be acti-
vated when the BIU executes the refresh bus cycle
Power-Save Control
The 80C186XL when in Enhanced Mode can enter
a power saving state by internally dividing the proc-
essor clock frequency by a programmable factor
This divided frequency is also available at the
CLKOUT pin
All internal logic including the Refresh Control Unit
and the timers have their clocks slowed down by
the division factor To maintain a real time count or a
fixed DRAM refresh rate these peripherals must be
re-programmed when entering and leaving the pow-
er-save mode
Interface for 80C187 Math
Coprocessor (80C186XL Only)
In Enhanced Mode three of the mid-range memory
chip selects are redefined according to Table 1 for
use with the 80C187 The fourth chip select MCS2
functions as in compatible mode and may be pro-
grammed for activity with ready logic and wait states
accordingly As in Compatible Mode MCS2 will func-
tion for one-fourth a programmed block size
Table 1 MCS Assignments
Compatible
Enhanced Mode
Mode
MCS0
PEREQ Processor Extension Request
MCS1
ERROR NPX Error
MCS2
MCS2
Mid-Range Chip Select
MCS3
NPS
Numeric Processor Select
ONCE Test Mode
To facilitate testing and inspection of devices when
fixed into a target system the 80C186XL has a test
mode available which allows all pins to be placed in
a high-impedance state ONCE stands for ‘‘ON Cir-
cuit Emulation’’ When placed in this mode the
80C186XL will put all pins in the high-impedance
state until RESET
The ONCE mode is selected by tying the UCS and
the LCS LOW during RESET These pins are sam-
pled on the low-to-high transition of the RES pin
The UCS and the LCS pins have weak internal pull-
up resistors similar to the RD and TEST BUSY pins
to guarantee ONCE Mode is not entered inadver-
tently during normal operation LCS and UCS must
be held low at least one clock after RES goes high
to guarantee entrance into ONCE Mode
7


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48 


数据表 下载

Go To PDF Page


链接网址




隐私政策
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn