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HUF76132P3 Datasheet(数据表) 6 Page - Fairchild Semiconductor |
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HUF76132P3 Datasheet(HTML) 6 Page - Fairchild Semiconductor |
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6 page 
©2003 Fairchild Semiconductor Corporation HUF76132P3, HUF76132S3S Rev. C1 FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 16. SWITCHING TIME vs GATE RESISTANCE Test Circuits and Waveforms FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18. UNCLAMPED ENERGY WAVEFORMS Typical Performance Curves Unless Otherwise Specified (Continued) COSS 2500 1500 0 05 15 25 2000 VDS, DRAIN TO SOURCE VOLTAGE (V) 1000 30 500 CISS CRSS 10 20 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 10 8 6 4 0 VDD = 15V 2 30 50 0 Qg, GATE CHARGE (nC) 10 ID = 75A ID = 51A ID = 25A WAVEFORMS IN DESCENDING ORDER: 20 40 100 20 30 40 50 0 400 300 200 0 10 RGS, GATE TO SOURCE RESISTANCE (Ω) VGS = 4.5V, VDD = 15V, ID = 41A, RL= 0.312Ω td(OFF) td(ON) tr tf 20 30 40 50 0 400 200 100 0 10 RGS, GATE TO SOURCE RESISTANCE (Ω) VGS = 10V, VDD = 15V, ID = 75A, RL= 0.20Ω 300 tr tf td(OFF) td(ON) tP VGS 0.01 Ω L IAS + - VDS VDD RG DUT VARY tP TO OBTAIN REQUIRED PEAK IAS 0V VDD VDS BVDSS tP IAS tAV 0 HUF76132P3, HUF76132S3S |
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