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HUF76129P3 Datasheet(数据表) 6 Page - Fairchild Semiconductor |
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HUF76129P3 Datasheet(HTML) 6 Page - Fairchild Semiconductor |
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6 page 
©2003 Fairchild Semiconductor Corporation HUF76129P3, HUF76129S3S Rev. B1 FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE NOTE: Refer to Fairchild Application Notes 7254 and 7260. FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 16. SWITCHING TIME vs GATE RESISTANCE Test Circuits and Waveforms FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18. UNCLAMPED ENERGY WAVEFORMS Typical Performance Curves (Continued) COSS 2000 1200 0 0 5 15 25 1600 VDS, DRAIN TO SOURCE VOLTAGE (V) 800 30 400 CISS CRSS 10 20 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 10 8 6 4 0 VDD = 15V 2 30 40 0 Qg, GATE CHARGE (nC) 10 ID = 56A ID = 35A ID = 20A WAVEFORMS IN DESCENDING ORDER: 20 100 20 30 40 50 0 400 300 200 0 10 RGS, GATE TO SOURCE RESISTANCE (Ω) td(OFF) td(ON) tr tf VGS = 4.5V, VDD = 15V, ID = 34A, RL = 0.441Ω 0 150 20 30 40 50 300 250 200 0 10 RGS, GATE TO SOURCE RESISTANCE (Ω) td(OFF) td(ON) tr tf VGS = 10V, VDD = 15V, ID = 56A, RL = 0.268Ω 50 100 tP VGS 0.01 Ω L IAS + - VDS VDD RG DUT VARY tP TO OBTAIN REQUIRED PEAK IAS 0V VDD VDS BVDSS tP IAS tAV 0 HUF76129P3, HUF76129S3S |
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