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HUF76107P3 Datasheet(数据表) 6 Page - Fairchild Semiconductor |
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HUF76107P3 Datasheet(HTML) 6 Page - Fairchild Semiconductor |
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6 page 
©2003 Fairchild Semiconductor Corporation HUF76107P3 Rev. B1 FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 16. SWITCHING TIME vs GATE RESISTANCE Test Circuits and Waveforms FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18. UNCLAMPED ENERGY WAVEFORMS Typical Performance Curves Unless otherwise specified (Continued) COSS 600 400 0 0 5 15 25 300 VDS, DRAIN TO SOURCE VOLTAGE (V) 200 30 100 CISS CRSS 10 20 500 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 10 8 6 4 0 VDD = 15V 2 810 0 Qg, GATE CHARGE (nC) 2 ID = 20A ID = 12A ID = 5A WAVEFORMS IN DESCENDING ORDER: 6 4 20 20 30 40 50 0 100 80 40 0 10 RGS, GATE TO SOURCE RESISTANCE (Ω) td(OFF) td(ON) tr tf VGS = 4.5V, VDD = 15V, ID = 10A, RL= 1.50Ω 60 40 20 30 40 50 0 100 80 60 0 10 RGS, GATE TO SOURCE RESISTANCE (Ω) td(OFF) td(ON) tf tr VGS = 10V, VDD = 15V, ID = 20A, RL= 0.75Ω 20 tP VGS 0.01 Ω L IAS + - VDS VDD RG DUT VARY tP TO OBTAIN REQUIRED PEAK IAS 0V VDD VDS BVDSS tP IAS tAV 0 HUF76107P3 |
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