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MT47H32M16CC3B 数据表(PDF) 17 Page - Micron Technology |
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MT47H32M16CC3B 数据表(HTML) 17 Page - Micron Technology |
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17 / 133 page  Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions (Continued) Symbol Type Description DQS, DQS# I/O Data strobe: Output with read data, input with write data for source synchronous oper- ation. Edge-aligned with read data, center-aligned with write data. DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. LDQS, LDQS# I/O Data strobe for lower byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, center-aligned with write data. LDQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. UDQS, UDQS# I/O Data strobe for upper byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, center-aligned with write data. UDQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. RDQS, RDQS# Output Redundant data strobe: For 64 Meg x 8 only. RDQS is enabled/disabled via the load mode command to the extended mode register (EMR). When RDQS is enabled, RDQS is output with read data only and is ignored during write data. When RDQS is disabled, ball B3 becomes data mask (see DM ball). RDQS# is only used when RDQS is enabled and dif- ferential data strobe mode is enabled. VDD Supply Power supply: 1.8V ±0.1V. VDDQ Supply DQ power supply: 1.8V ±0.1V. Isolated on the device for improved noise immunity. VDDL Supply DLL power supply: 1.8V ±0.1V. VREF Supply SSTL_18 reference voltage (VDDQ/2). VSS Supply Ground. VSSDL Supply DLL ground: Isolated on the device from VSS and VSSQ. VSSQ Supply DQ ground: Isolated on the device for improved noise immunity. NC – No connect: These balls should be left unconnected. NF – No function: x8: these balls are used as DQ[7:4]; x4: they are no function. NU – Not used: If EMR(E10) = 0: x16, A8 = UDQS# and E8 = LDQS#; x8, A2 = RDQS# and A8 = DQS#; x4, A2 = NU and A8 = NU. If EMR(E10) = 1: x16, A8 = NU and E8 = NU; x8, A2 = NU and A8 = NU; x4, A2 = NU and A8 = NU. RFU – Reserved for future use: Bank address BA2, row address bits A13 (x16 only), A14, and A15. 512Mb: x4, x8, x16 DDR2 SDRAM Ball Assignments and Descriptions PDF: 09005aef82f1e6e2 512MbDDR2.pdf - Rev. T 2/12 EN 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. |
类似零件编号 - MT47H32M16CC3B |
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类似说明 - MT47H32M16CC3B |
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