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AD8402ARUZ10 数据表(PDF) 3 Page - Analog Devices |
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AD8402ARUZ10 数据表(HTML) 3 Page - Analog Devices |
3 / 32 page AD8400/AD8402/AD8403 Rev. E | Page 3 of 32 GENERAL DESCRIPTION (continued from Page 1) Each VR has its own VR latch that holds its programmed resistance value. These VR latches are updated from an SPI- compatible, serial-to-parallel shift register that is loaded from a standard 3-wire, serial-input digital interface. Ten data bits make up the data-word clocked into the serial input register. The data-word is decoded where the first two bits determine the address of the VR latch to be loaded, and the last eight bits are the data. A serial data output pin at the opposite end of the serial register allows simple daisy chaining in multiple VR applications without additional external decoding logic. The reset (RS) pin forces the wiper to midscale by loading 80H into the VR latch. The SHDN pin forces the resistor to an end- to-end open-circuit condition on the A terminal and shorts the wiper to the B terminal, achieving a microwatt power shutdown state. When SHDN is returned to logic high, the previous latch settings put the wiper in the same resistance setting prior to shutdown. The digital interface is still active in shutdown so that code changes can be made that will produce new wiper positions when the device is taken out of shutdown. The AD8400 is available in the SOIC-8 surface mount. The AD8402 is available in both surface-mount (SOIC-14) and 14-lead PDIP packages, while the AD8403 is available in a narrow-body, 24-lead PDIP and a 24-lead, surface-mount package. The AD8402/AD8403 are also offered in the 1.1 mm thin TSSOP-14/TSSOP-24 packages for PCMCIA applications. All parts are guaranteed to operate over the extended industrial temperature range of −40°C to +125°C. |
类似零件编号 - AD8402ARUZ10 |
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类似说明 - AD8402ARUZ10 |
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