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EPM3064ATC44-4N 数据表(PDF) 30 Page - Altera Corporation |
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EPM3064ATC44-4N 数据表(HTML) 30 Page - Altera Corporation |
30 / 46 page 30 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet tPIA PIA delay (2) 0.9 1.5 2.1 ns tLPA Low–power adder (5) 2.5 4.0 5.0 ns Table 18. EPM3064A External Timing Parameters Note (1) Symbol Parameter Conditions Speed Grade Unit –4 –7 –10 Min Max Min Max Min Max tPD1 Input to non–registered output C1 = 35 pF (2) 4.5 7.5 10.0 ns tPD2 I/O input to non–registered output C1 = 35 pF (2) 4.5 7.5 10.0 ns tSU Global clock setup time (2) 2.8 4.7 6.2 ns tH Global clock hold time (2) 0.0 0.0 0.0 ns tCO1 Global clock to output delay C1 = 35 pF 1.0 3.1 1.0 5.1 1.0 7.0 ns tCH Global clock high time 2.0 3.0 4.0 ns tCL Global clock low time 2.0 3.0 4.0 ns tASU Array clock setup time (2) 1.6 2.6 3.6 ns tAH Array clock hold time (2) 0.3 0.4 0.6 ns tACO1 Array clock to output delay C1 = 35 pF (2) 1.04.3 1.07.2 1.09.6 ns tACH Array clock high time 2.0 3.0 4.0 ns tACL Array clock low time 2.0 3.0 4.0 ns tCPPW Minimum pulse width for clear and preset (3) 2.0 3.0 4.0 ns tCNT Minimum global clock period (2) 4.5 7.4 10.0 ns fCNT Maximum internal global clock frequency (2), (4) 222.2 135.1 100.0 MHz tACNT Minimum array clock period (2) 4.5 7.4 10.0 ns fACNT Maximum internal array clock frequency (2), (4) 222.2 135.1 100.0 MHz Table 17. EPM3032A Internal Timing Parameters (Part 2 of 2) Note (1) Symbol Parameter Conditions Speed Grade Unit –4 –7 –10 Min Max Min Max Min Max |
类似零件编号 - EPM3064ATC44-4N |
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类似说明 - EPM3064ATC44-4N |
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