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EP20K100EQI240-2X 数据表(PDF) 33 Page - Altera Corporation |
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EP20K100EQI240-2X 数据表(HTML) 33 Page - Altera Corporation |
33 / 117 page Altera Corporation 33 APEX 20K Programmable Logic Device Family Data Sheet Input/Output Clock Mode The input/output clock mode contains two clocks. One clock controls all registers for inputs into the ESB: data input, WE, RE, read address, and write address. The other clock controls the ESB data output registers. The ESB also supports clock enable and asynchronous clear signals; these signals also control the reading and writing of registers independently. Input/output clock mode is commonly used for applications where the reads and writes occur at the same system frequency, but require different clock enable signals for the input and output registers. Figure 21 shows the ESB in input/output clock mode. Figure 21. ESB in Input/Output Clock Mode Note (1) Notes to Figure 21: (1) All registers can be cleared asynchronously by ESB local interconnect signals, global signals, or the chip-wide reset. (2) APEX 20KE devices have four dedicated clocks. Single-Port Mode The APEX 20K ESB also supports a single-port mode, which is used when simultaneous reads and writes are not required. See Figure 22. Dedicated Clocks 2 or 4 4 D ENA Q D ENA Q D ENA Q D ENA Q D ENA Q data[ ] rdaddress[ ] wraddress[ ] RAM/ROM 128 × 16 256 × 8 512 × 4 1,024 × 2 2,048 × 1 Data In Read Address Write Address Read Enable Write Enable Data Out outclken inclken inclock outclock D ENA Q Write Pulse Generator rden wren Dedicated Inputs & Global Signals to MegaLAB, FastTrack & Local Interconnect (2) |
类似零件编号 - EP20K100EQI240-2X |
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类似说明 - EP20K100EQI240-2X |
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