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EP4CE6F17C7N 数据表(PDF) 39 Page - Altera Corporation |
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EP4CE6F17C7N 数据表(HTML) 39 Page - Altera Corporation |
39 / 42 page Chapter 1: Cyclone IV Device Datasheet 1–39 Glossary May 2013 Altera Corporation Cyclone IV Device Handbook, Volume 3 R RL Receiver differential input discrete resistor (external to Cyclone IV devices). Receiver Input Waveform Receiver input waveform for LVDS and LVPECL differential standards: Receiver input skew margin (RSKM) High-speed I/O block: The total margin left after accounting for the sampling window and TCCS. RSKM = (TUI – SW – TCCS) / 2. S Single-ended voltage- referenced I/O Standard The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver changes to the new logic state. The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing. SW (Sampling Window) High-speed I/O block: The period of time during which the data must be valid to capture it correctly. The setup and hold times determine the ideal strobe position in the sampling window. Table 1–46. Glossary (Part 3 of 5) Letter Term Definitions Single-Ended Waveform Differential Waveform (Mathematical Function of Positive & Negative Channel) Positive Channel (p) = V IH Negative Channel (n) = V IL Ground V ID V ID 0 V V CM p - n V ID VIH(AC) VIH(DC) VREF VIL(DC) VIL(AC) VOH VOL VCCIO VSS |
类似零件编号 - EP4CE6F17C7N |
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类似说明 - EP4CE6F17C7N |
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