 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
EP1K50QC208-3 数据表(PDF) 32 Page - Altera Corporation |
|
||||||||||||||||||||||||||||||
EP1K50QC208-3 数据表(HTML) 32 Page - Altera Corporation |
|
|
32 / 86 page  32 Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet When dedicated inputs drive non-inverted and inverted peripheral clears, clock enables, and output enables, two signals on the peripheral control bus will be used. Table 7 lists the sources for each peripheral control signal and shows how the output enable, clock enable, clock, and clear signals share 12 peripheral control signals. Table 7 also shows the rows that can drive global signals. Signals on the peripheral control bus can also drive the four global signals, referred to as GLOBAL0 through GLOBAL3. An internally generated signal can drive a global signal, providing the same low-skew, low-delay characteristics as a signal driven by an input pin. An LE drives the global signal by driving a row line that drives the peripheral bus which then drives the global signal. This feature is ideal for internally generated clear or clock signals with high fan-out. However, internally driven global signals offer no advantage over the general-purpose interconnect for routing data signals. The chip-wide output enable pin is an active-high pin that can be used to tri-state all pins on the device. This option can be set in the Altera software. The built-in I/O pin pull-up resistors (which are active during configuration) are active when the chip-wide output enable pin is asserted. The registers in the IOE can also be reset by the chip-wide reset pin. Table 7. Peripheral Bus Sources for ACEX Devices Peripheral Control Signal EP1K10 EP1K30 EP1K50 EP1K100 OE0 Row ARow ARow ARow A OE1 Row A Row B Row B Row C OE2 Row B Row C Row D Row E OE3 Row B Row D Row F Row L OE4 Row C Row E Row H Row I OE5 Row C Row F Row J Row K CLKENA0 /CLK0/GLOBAL0 Row A Row A Row A Row F CLKENA1 /OE6/GLOBAL1 Row A Row B Row C Row D CLKENA2 /CLR0 Row B Row C Row E Row B CLKENA3 /OE7/GLOBAL2 Row B Row D Row G Row H CLKENA4 /CLR1 Row C Row E Row I Row J CLKENA5 /CLK1/GLOBAL3 Row C Row F Row J Row G |
类似零件编号 - EP1K50QC208-3 |
|
类似说明 - EP1K50QC208-3 |
|
|
链接网址 |
| 隐私政策 |
| ALLDATASHEETCN.COM |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
