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MT46V64M4 数据表(PDF) 13 Page - Micron Technology |
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MT46V64M4 数据表(HTML) 13 Page - Micron Technology |
13 / 91 page PDF: 09005aef80768abb/Source: 09005aef82a95a3a Micron Technology, Inc., reserves the right to change products or specifications without notice. 256Mb_DDR_x4x8x16_D2.fm - 256Mb DDR: Rev. S, Core DDR: Rev. E 9/12 EN 13 ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x4, x8, x16 DDR SDRAM Pin and Ball Assignments and Descriptions Table 1: Pin and Ball Descriptions Symbol Type Description A[12:0] Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[1:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE REGISTER command. BA[1:0] Input Bank address inputs: BA[1:0] define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA[1:0] also define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER (LMR) command. CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data (DQ and DQS) is referenced to the crossings of CK and CK#. CKE Input Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers, and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle) or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for POWER-DOWN entry and exit and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK#, and CKE) are disabled during POWER- DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied and until CKE is first brought HIGH, after which it becomes a SSTL_2 input only. CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. DM LDM, UDM Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. For x16 devices, LDM is DM for DQ[7:0], and UDM is DM for DQ[15:8]. Pin 20 is NC on x4 and x8 devices. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered. DQ[15:0] I/O Data input/output: Data bus for x16 devices. DQ[7:0] I/O Data input/output: Data bus for x8 devices. DQ[3:0] I/O Data input/output: Data bus for x4 devices. DQS LDQS, UDQS I/O Data strobe: Output with read data; input with write data. DQS is edge-aligned with read data; centered in write data. It is used to capture data. For x16 devices, LDQS is DQS for DQ[7:0], and UDQS is DQS for DQ[15:8]. Pin 16 (E7) is NC for x4 and x8 devices. VDD Supply Power supply. VDDQ Supply DQ power supply: Isolated on the die for improved noise immunity. VSS Supply Ground. VSSQ Supply DQ ground: Isolated on the die for improved noise immunity. VREF Supply SSTL_2 reference voltage. NC – No connect for x16, x8, x4: These pins should be left unconnected. DNU – Do not use: Must float to minimize noise on VREF. |
类似零件编号 - MT46V64M4 |
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类似说明 - MT46V64M4 |
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