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HCPL-3180 数据表(PDF) 11 Page - AVAGO TECHNOLOGIES LIMITED |
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HCPL-3180 数据表(HTML) 11 Page - AVAGO TECHNOLOGIES LIMITED |
11 / 16 page 11 Figure25.RecommendedLEDdriveandapplicationcircuitforHCPL-3180. Figure23.tPLH,tPHL,trandtftestcircuitandwaveform. Figure24.CMRtestcircuitandwaveform. ApplicationsInformationEliminatingNegativeIGBTGate Drive To keep the IGBT firmly off, the HCPL-3180 has a very low maximum VOL specification of 0.4 V. The HCPL-3180 realizes the very low VOL by using a DMOS transistor with 1 W (typical) on resistance in its pull down circuit. When the HCPL-3180 is in the low state, the IGBT gate is shorted to the emitter by Rg + 1 W. Minimizing Rg and the lead inductance from the HCPL-3180 to the IGBT gate and emitter (possibly by mounting HCPL-3180 on a small PC board directly above the IGBT) can eliminate the need for negative IGBT gate drive in many applications as shown in Figure 25. Care should be taken with such a PC board design to avoid routing the IGBT collector or emitter traces close to the HCPL-3180 input as this can result in unwanted coupling of transient signals into the input of HCPL-3180 and degrade performance. (If the IGBT drain must be routed near the HCPL-3180 input, then the LED should be reverse biased when in the off state to prevent the transient signals coupled from the IGBT drain from turning on the HCPL-3180.) 0.1 µF VCC = 20 V 10 Ω 1 3 IF = 10 to 16 mA VO + – + – 2 4 8 6 7 5 250 KHz 50% DUTY CYCLE 500 Ω 10 nF IF VOUT tPHL tPLH tf tr 10% 50% 90% 0.1 µF VCC = 20 V 1 3 IF VO + – + – 2 4 8 6 7 5 A + B VCM = 1500 V 5 V VCM ∆t 0 V VO SWITCH AT B: IF = 0 mA VO SWITCH AT A: IF = 10 mA VOL VOH ∆t VCM δV δt = + HVDC 3-PHASE AC - HVDC 0.1 µF VCC = 15 V 1 3 + – 2 4 8 6 7 5 270 Ω +5 V CONTROL INPUT Rg Q1 Q2 74XXX OPEN COLLECTOR |
类似零件编号 - HCPL-3180 |
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类似说明 - HCPL-3180 |
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