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N25Q032A13ESE40F 数据表(PDF) 67 Page - Micron Technology |
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N25Q032A13ESE40F 数据表(HTML) 67 Page - Micron Technology |
67 / 153 page N25Q032 - 3 V Instructions 67/153 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. All rights reserved. 9.1.13 Dual Input Fast Program (DIFP) The Dual Input Fast Program (DIFP) instruction is very similar to the Page Program (PP) instruction, except that the data are entered on two pins (pin DQ0 and pin DQ1) instead of only one. Inputting the data on two pins instead of one doubles the data transfer bandwidth compared to the Page Program (PP) instruction. The Dual Input Fast Program (DIFP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data input (DQ0). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that go beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes in the same page. For optimized timings, it is recommended to use the Dual Input Fast Program (DIFP) instruction to program all consecutive targeted bytes in a single sequence rather to using several Dual Input Fast Program (DIFP) sequences each containing only a few bytes. See Table 31.: AC Characteristics. Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Dual Input Fast Program (DIFP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Dual Input Fast Program (DIFP) cycle is in progress, the Status Register and the Flag Status Register may be read to check if the internal modify cycle is finished. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Dual Input Fast Program (DIFP) instruction applied to a page that belongs to a hardware or software protected sector is not executed. Dual Input Fast Program cycle can be paused by mean of Program/Erase Suspend (PES) instruction and resumed by mean of Program/Erase Resume (PER) instruction. |
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类似说明 - N25Q032A13ESE40F |
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