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N25Q032A13ESC40G 数据表(PDF) 3 Page - Micron Technology

部件名 N25Q032A13ESC40G
功能描述  32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface
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制造商  MICRON [Micron Technology]
网页  http://www.micron.com
标志 MICRON - Micron Technology

N25Q032A13ESC40G 数据表(HTML) 3 Page - Micron Technology

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M25Q032 - 3 V
Contents
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
5.2.2
Dual Command Fast reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2.3
Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2.4
Subsector Erase, Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . 27
5.2.5
Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . 27
5.2.6
Read and Modify registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2.7
Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . 27
5.2.8
HOLD (or Reset) condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3
Quad SPI (QIO-SPI)Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3.1
Multiple I/O Read Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3.2
Quad Command Fast reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3.3
QUAD Command Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3.4
Subsector Erase, Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . 29
5.3.5
Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . 29
5.3.6
Read and Modify registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.3.7
Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . 30
5.3.8
HOLD (or Reset) condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3.9
VPP pin Enhanced Supply Voltage feature . . . . . . . . . . . . . . . . . . . . . . 30
6
Volatile and Non Volatile Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1
Legacy SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1.1
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1.2
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1.3
Block Protect bits (BP2, BP1, BP0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1.4
TB bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1.5
SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2
Non Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2.1
Dummy clock cycles NV configuration bits (NVCR bits from 15 to 12) . 36
6.2.2
XIP NV configuration bits (NVCR bits from 11 to 9) . . . . . . . . . . . . . . . . 37
6.2.3
Output Driver Strength NV configuration bits (NVCR bits from 8 to 6) . . 37
6.2.4
Hold (Reset) disable NV configuration bit (NVCR bit 4) . . . . . . . . . . . . 37
6.2.5
Quad Input NV configuration bit (NVCR bit 3) . . . . . . . . . . . . . . . . . . . . 37
6.2.6
Dual Input NV configuration bit (NVCR bit 2) . . . . . . . . . . . . . . . . . . . . . 37
6.3
Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.3.1
Dummy clock cycle: VCR bits 7:4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3.2
XIP Volatile Configuration bits (VCR bit 3) . . . . . . . . . . . . . . . . . . . . . . . 39
6.3.3
Wrap: VCR bits 1:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.4
Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . 39


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