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N25Q032A13ESC40F Datasheet(数据表) 42 Page - Micron Technology

部件型号  N25Q032A13ESC40F
说明  32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface
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制造商  MICRON [Micron Technology]
网页  http://www.micron.com
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N25Q032A13ESC40F Datasheet(HTML) 42 Page - Micron Technology

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Volatile and Non Volatile Registers
N25Q032 - 3 V
42/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
6.4.5
Output Driver Strength VECR<2:0>
The bits from 2 to 0 of the VECR set the value of the output driver strength, enabling to
optimize the impedance at Vcc/2 output voltage for the specific application as described in
Table 7.: Volatile Enhanced Configuration Register.
The default values of Output Driver Strength is set by the dedicated bits of the Non Volatile
Configuration Register (NVCR), the parts are delivered with the output impedance at Vcc/2
equal to 30 Ohms.
6.5
Flag Status Register
The Flag Status Register is a powerful tool to investigate the status of the device, checking
information regarding what is actually doing the memory and detecting possible error
conditions.
The Flag status register is composed by 8 bit.Three bits (Program/Erase Controller bit,
Erase Suspend bit and Program Suspend bit) are a “Status Indicator bit”, they are set and
reset automatically by the memory. Four bits (Erase error bit, Program error bit, VPP 1 to 0
error bit and Protection error bit) are “Error Indicators bits”, they are set by the memory
when some program or erase operation fails or the user tries to perform a forbidden
operation. The user can clear the Error Indicators bits by mean of the Clear Flag Status
Register (CLFSR) instruction.
All the Flag Status Register bits can be read by mean of the Read Status Register (RFSR)
instruction.
6.5.1
P/E Controller Status bit
The bit 7 of the Flag Status register represents the Program/Erase Controller Status bit, It
indicates whether there is a Program/Erase internal cycle active. When P/E Controller
Status bit is Low (FSR<7>=0) the device is busy; when the bit is High (FSR<7>=1) the
device is ready to process a new command.
This bit has the same meaning of Write In Progress (WIP) bit of the standard SPI Status
Register, but with opposite logic: FSR<7> = not WIP
It's possible to make the polling instructions, to check if the internal modify operations are
finished, both on the Flag Status register bit 7 or on WIP bit of the Status Register.
Table 8.
Flag Status Register
BIT
Description
Note
7
P/E Controller (not WIP)
Status
6
Erase Suspend
Status
5
Erase
Error
4
Program
Error
3
VPP
Error
2
Program Suspend
Status
1
Protection
Error
0
RESERVED




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