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N25Q032A13ESC40F Datasheet(数据表) 13 Page - Micron Technology

部件型号  N25Q032A13ESC40F
说明  32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface
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制造商  MICRON [Micron Technology]
网页  http://www.micron.com
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N25Q032A13ESC40F Datasheet(HTML) 13 Page - Micron Technology

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N25Q032 - 3 V
Description
13/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
The N25Q032 has 64 one-time-programmable bytes (OTP bytes) that can be read and
programmed using two dedicated instructions, Read OTP (ROTP) and Program OTP
(POTP), respectively. These 64 bytes can be permanently locked by a particular Program
OTP (POTP) sequence. Once they have been locked, they become read-only and this state
cannot be reversed.
Many different N25Q032 configurations are available, please refer to the ordering scheme
page for the possibilities. Additional features are available as security options (The Security
features are described in a dedicated Application Note). Please contact your nearest
Numonyx Sales office for more information.
Figure 1.
Logic diagram
Note:
Reset functionality is available in devices with a dedicated part number. See Section 16:
Ordering information.
Note:
There is an exposed central pad on the underside of the MLP8 package. This is pulled,
internally, to VSS, and must not be allowed to be connected to any other voltage or signal
line on the PCB.
Logic_Diagram_x25x
S
VCC
HOLD/DQ3
VSS
DQ1
C
DQ0
W/VPP/DQ2
Table 1.
Signal names
Signal
Description
I/O
C
Serial Clock
Input
DQ0
Serial Data input
I/O(1)
DQ1
Serial Data output
I/O(2)
S
Chip Select
Input
W/VPP/DQ2
Write Protect/Enhanced Program supply voltage/additional data I/O
I/O(3)
HOLD/DQ3(4)
Hold (Reset function available upon customer request)/additional data I/O
I/O(3)
VCC
Supply voltage
VSS
Ground
1.
Provides dual and quad I/O for Extended SPI protocol instructions, dual I/O for Dual I/O SPI protocol instructions, and
quad I/O for Quad I/O SPI protocol instructions.
2.
Provides dual and quad instruction input for Extended SPI protocol, dual instruction input for Dual I/O SPI protocol, and
quad instruction input for Quad I/O SPI protocol.
3. Provides quad I/O for Extended SPI protocol instructions, and quad I/O for Quad I/O SPI protocol instructions.
4. Reset functionality available with a dedicated part number. See Section 16: Ordering information.




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