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N25Q032A13ESC40F Datasheet(数据表) 98 Page - Micron Technology

部件型号  N25Q032A13ESC40F
说明  32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface
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制造商  MICRON [Micron Technology]
网页  http://www.micron.com
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N25Q032A13ESC40F Datasheet(HTML) 98 Page - Micron Technology

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Instructions
N25Q032 - 3 V
98/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Figure 60.
Read Lock Register instruction and data-out sequence DIO-SPI
*Address bits A23 and A22 are “Don’t Care.”
9.2.17
Write to Lock Register (WRLR)
The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock
Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed.
Except for the parallelizing of the instruction code, the address and the input data on the two
pins DQ0 and DQ1, the instruction functionality is exactly the same as the Write to Lock
Register (WRLR) instruction of the Extended SPI protocol.
Figure 61.
Write to Lock Register instruction sequence DIO-SPI
*Address bits A23 and A22 are “Don’t Care.”
9.2.18
Read Flag Status Register
The Read Flag Status Register (RFSR) instruction allows the Flag Status Register to be
read.
Except for the parallelizing of the instruction code and the output data on the two pins DQ0
and DQ1, the instruction functionality is exactly the same as the Read Flag Status Register
(RFSR) instruction of the Extended SPI protocol.
Instruction
24-Bit Address*
Lock Register Out
12 13 14 15
DQ0
DQ1
S
C
2
1
34567
8
9
10 11
0
22 20 18 16
23 21 19 17
14 12 10
8
15 13 11
9
642064
0
2
753175
1
3
16 17 18 19
Instruction
*24-bit Address
Lock Register In
12 13 14 15
DQ0
DQ1
S
C
2
1
34567
8
9
10 11
0
22 20 18 16
23 21 19 17
14 12 10
8
15 13 11
9
642064
0
2
753175
1
3
12 13 14 15




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