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N25Q032A13ESC40F Datasheet(数据表) 97 Page - Micron Technology

部件型号  N25Q032A13ESC40F
说明  32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface
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制造商  MICRON [Micron Technology]
网页  http://www.micron.com
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N25Q032A13ESC40F Datasheet(HTML) 97 Page - Micron Technology

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N25Q032 - 3 V
Instructions
97/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Figure 58.
Read Status Register instruction sequence DIO-SPI
9.2.15
Write status register (WRSR)
The write status register (WRSR) instruction allows new values to be written to the status
register. Before it can be accepted, a write enable (WREN) instruction must previously have
been executed. Except for the parallelizing of the instruction code and the input data on the
two pins DQ0 and DQ1, the instruction functionality and the protection feature management
is exactly the same as the Write Status Register (WRSR) instruction of the Extended SPI
protocol.
Figure 59.
Write Status Register instruction sequence DIO-SPI
*Address bits A[23:22] are “Don’t Care.”
9.2.16
Read Lock Register (RDLR)
The Read Lock Register instruction is used to read the lock register content.
Except for the parallelizing of the instruction code, the address and the output data on the
two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Read Lock
Register (RDLR) instruction of the Extended SPI protocol.
Status Register Out
DQ0
DQ1
Dual_Read_SR
Instruction
Byte
Byte
S
C
2
1
34567
8
9
10 11
0
6420
7531
6420
7531
Status Register In
DQ0
DQ1
Instruction
Byte
S
C
2
1
34567
0
6420
7531




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