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N25Q032A13ESC40F Datasheet(数据表) 91 Page - Micron Technology

部件型号  N25Q032A13ESC40F
说明  32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface
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制造商  MICRON [Micron Technology]
网页  http://www.micron.com
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N25Q032A13ESC40F Datasheet(HTML) 91 Page - Micron Technology

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N25Q032 - 3 V
Instructions
91/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
9.2.4
Read OTP (ROTP)
The Read OTP (ROTP) instruction is used to read the 64 bytes OTP area in the DIO-SPI
protocol. The instruction functionality is exactly the same as the Read OTP instruction of the
Extended SPI protocol; the only difference is that in the DIO-SPI protocol instruction code,
address and output data are all parallelized on the two pins DQ0 and DQ1.
Note:
The dummy bits can not be parallelized since these clock cycles are requested to perform
the internal reading operation.
Figure 46.
Read OTP instruction and data-out sequence DIO-SPI
9.2.5
Write Enable (WREN)
The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit.
Except for the parallelizing of the instruction code on the two pins DQ0 and DQ1, the
instruction functionality is exactly the same as the Write Enable (WREN) instruction of the
Extended SPI protocol.
Figure 47.
Write Enable instruction sequence DIO-SPI
9.2.6
Write Disable (WRDI)
The Write Disable (WRDI) instruction resets the Write Enable Latch (WEL) bit.
Instruction
24-bit Address
DQ0
DQ1
S
C
22 20 18 16
23 21 19 17
14 12 10
8
15 13 11
9
6420
7531
MSB
MSB
75
1
3
64
0
2
Data Out 1
64
0
2
Data Out n
75
1
3
12 13 14 15
2
1
34567
8
9
10 11
0
16 17 18 19 20 21 22 23 24 25 26 27 28
Dummy cycles
C
DQ0
DQ1
2
13
4
0
S
Instruction




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