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N25Q032A13ESC40F Datasheet(数据表) 90 Page - Micron Technology

部件型号  N25Q032A13ESC40F
说明  32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface
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制造商  MICRON [Micron Technology]
网页  http://www.micron.com
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N25Q032A13ESC40F Datasheet(HTML) 90 Page - Micron Technology

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Instructions
N25Q032 - 3 V
90/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Note:
The dummy bits can not be parallelized since these clock cycles are requested to perform
the internal reading operation.
Figure 44.
Dual Read Serial Flash Discovery Parameter
*Address bits A[23:11] are “Don’t Care.”
9.2.3
Dual Command Fast Read (DCFR)
The Dual Command Fast Read (DCFR) instruction allows to read the memory in DIO-SPI
protocol, parallelizing the instruction code, the address and the output data on two pins
(DQ0 and DQ1). The Dual Command Fast Read (DCFR) instruction can be issued, when
the device is set in DIO-SPI mode, by sending to the memory indifferently one of the 3
instructions codes: 0Bh, 3Bh or BBh, the effect is exactly the same. The 3 instruction codes
are all accepted to help the application code porting from Extended SPI protocol to DIO-SPI
protocol.
Apart for the parallelizing on two pins of the instruction code, the Dual Command Fast Read
instruction functionality is exactly the same as the Dual I/O Fast Read of the Extended SPI
protocol.
Figure 45.
Dual Command Fast Read instruction and data-out sequence DIO-SPI
*Address bits A23 and A22 are “Don’t Care.”
Instruction
*24-Bit Address
DQ0
DQ1
S
C
22 20 18 16
23 21 19 17
14 12 10
8
15 13 11
9
6420
7531
MSB
MSB
75
1
3
64
0
2
Data Out 1
64
0
2
Data Out n
75
1
3
12 13 14 15
2
1
34567
8
9
10 11
0
16 17 18 19 20 21 22 23 24 25 26 27 28
Dummy cycles
The dummy clock cycle depends on the dummy clock configuration in the NVCR/VCR register (default = 8).
Instruction
*24-bit Address
DQ0
DQ1
S
C
22 20 18 16
23 21 19 17
14 12 10
8
15 13 11
9
6420
7531
MSB
MSB
75
1
3
64
0
2
Data Out 1
64
0
2
Data Out n
75
1
3
12 13 14 15
2
1
34567
8
9
10 11
0
16 17 18 19 20 21 22 23 24 25 26 27 28
Dummy cycles




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