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N25Q032A13ESC40F Datasheet(数据表) 78 Page - Micron Technology

部件型号  N25Q032A13ESC40F
说明  32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface
下载  153 Pages
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制造商  MICRON [Micron Technology]
网页  http://www.micron.com
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N25Q032A13ESC40F Datasheet(HTML) 78 Page - Micron Technology

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Instructions
N25Q032 - 3 V
78/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
9.1.22
Program/Erase Resume
After a Program/Erase suspend instruction, a Program/Erase Resume instruction is
required to continue performing the suspended Program or Erase sequence.
Program/Erase Resume instruction is ignored if the device is not in a Program/Erase
Suspended status. The WIP bit of the Status Register and Program/Erase controller bit (Not
WIP) of the Flag Status Register both switch to the busy state (1 and 0 respectively) after
Program/Erase Resume instruction until the Program or Erase sequence is completed.
In this case the next Program/Erase Resume Instruction resumes the more recent
suspended modify cycle, and another Program/Erase Resume Instruction is needed to
resume also the former modify cycle.
9.1.23
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Program, Erase or Write Status
Register cycle is in progress. When one of these cycles is in progress, it is recommended to
check the Write In Progress (WIP) bit (or the Program/Erase controller bit of the Flag Status
Register) before sending a new instruction to the device. It is also possible to read the
Status Register continuously, as shown here.
Figure 31.
Read Status Register instruction sequence
9.1.24
Write status register (WRSR)
The write status register (WRSR) instruction allows new values to be written to the status
register. Before it can be accepted, a write enable (WREN) instruction must previously have
been executed. After the write enable (WREN) instruction has been decoded and executed,
the device sets the write enable latch (WEL).
The write status register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on serial data input (DQ0).
The write status register (WRSR) instruction has no effect on b1 and b0 of the status
register.
Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.
If not, the write status register (WRSR) instruction is not executed. As soon as Chip Select
(S) is driven High, the self-timed write status register cycle (whose duration is tW) is
C
DQ0
S
2
1
3456789 10 11 12 13 14 15
Instruction
0
DQ1
7
6543210
Status register out
High Impedance
MSB
7
6543210
Status register out
MSB
7




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