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N25Q032A13ESC40F Datasheet(数据表) 55 Page - Micron Technology

部件型号  N25Q032A13ESC40F
说明  32-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface
下载  153 Pages
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制造商  MICRON [Micron Technology]
网页  http://www.micron.com
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N25Q032A13ESC40F Datasheet(HTML) 55 Page - Micron Technology

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N25Q032 - 3 V
Instructions
55/153
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
9.1.1
Read Identification (RDID)
The Read Identification (RDID) instruction allows to read the device identification data:
Manufacturer identification (1 byte)
Device identification (2 bytes)
A Unique ID code (UID) (17 bytes, of which 14 are factory programmed
The manufacturer identification is assigned by JEDEC, and has the value 20h. The device
identification is assigned by the device manufacturer, and indicates the memory type in the
first byte (BAh), and the memory capacity of the device in the second byte (16h). The UID is
composed by 17 read only bytes, containing the length of the following data in the first byte
(set to 10h), 2 bytes of Extended Device ID (EDID) to identify the specific device
configuration (Top, Bottom or uniform architecture, Hold or Reset functionality), and 14
bytes of the optional Customized Factory Data (CFD) content. The CFD bytes are factory
programmed with specific data for each device.
Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is
not decoded, and has no effect on the cycle that is in progress.
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code
for the instruction is shifted in. After this, the 24-bit device identification, stored in the
memory, the 17 bytes of UID content will be shifted out on Serial Data output (DQ1). Each
bit is shifted out during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 10.
The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at
any time during data output.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in
the Standby Power mode, the device waits to be selected, so that it can receive, decode and
execute instructions.
RDVECR
Read Volatile Enhanced Configuration
Register
0110 0101
65h
0
0
1 to
WRVECR
Write Volatile Enhanced Configuration
Register
0110 0001
61h
0
0
1
1.
The Number of dummy clock cycles is configurable by user
Table 13.
Instruction set: extended SPI protocol (page 2 of 2)
Instruction
Description
One-byte
Instruction
Code (BIN)
One-byte
Instruction
Code
(HEX)
Address
bytes
Dummy
clock
cycle
Data
bytes
Table 14.
Read Identification data-out sequence
Manufacturer
Identification
Device identification
UID
Memory type
Memory capacity
EDID+CFD length
EDID
CFD
20h
BAh
16h
10h
2 bytes
14 bytes




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